AM625 datasheet(150/255 Pages) TI

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For GPMC_FCLK_MUX:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:

•

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/

WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,

OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)

For no extra_delay:

•

GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed

•

GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed

•

GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed

•

GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed

GPMC_CLK

GPMC_CSn[i]

GPMC_A[MSB:1]

GPMC_BE0n_CLE

GPMC_BE1n

GPMC_ADVn_ALE

GPMC_OEn_REn

GPMC_AD[15:0]

GPMC_WAIT[j]

Valid Address

D 0

F12

F13

F11

F19

F18

F20

F10

F19

F12

GPMC_01

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 7-46. GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)

AM625, AM623

SPRSP58A – JUNE 2022 – REVISED NOVEMBER 2022

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