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Table 9-3. Recommended Center Tapped Transformers for SN6507-Q1

(continued)

APPLICATIO

TURNS

RATIO

(1:N)

V-t

product

Min (Vμs)

ISOLATIO

N (VRMS)

DIMENSION (mm)

(L,W,H)

PART NUMBER 1

24 V→ 30 V

1.4

2.5 k

(10.3, 12.07, 5.97)

Coilcraft TX1-ZC1891-

1.4

2.5 k

(8.5, 12.87, 5.16)

Wurth 750319948

1.43

36.1

2.5 k

(11, 13.5, 10.54)

Semitel EP7-818

12 V→ 30 V

2.6

2.5 k

(8.5, 12.87, 5.16)

Wurth 750319949

2.8

2.5 k

(10.3, 12.07, 5.97)

Coilcraft TX1-ZC1892-

2.8

25.8

2.5 k

(11, 13.5, 10.54)

Semitel EP7-816

24 V→ 24 V

1.09

2.5 k

(8.5, 12.87, 5.16)

Wurth 750319697

24 V→ 12 V

0.55

2.5 k

(8.5, 12.87, 5.16)

Wurth 750319695

0.625

3.75 k

(10.3, 13.2, 12.5)

Pulse PAG6356.085NLT

24 V→ 5 V

0.27

2.5 k

(8.5, 12.87, 5.16)

Wurth 750319694

0.25

3.75 k

(10.3, 13.2, 12.5)

Pulse PAG6356.082NLT

12 V→ 24 V

2.13

7.5

2.5 k

(8.5, 12.87, 5.16)

Wurth 750319693

12 V→ 12 V

1.13

7.5

2.5 k

(8.5, 12.87, 5.16)

Wurth 750319691

12 V→ 5 V

0.5

7.5

2.5 k

(8.5, 12.87, 5.16)

Wurth 750319690

24 V→ 3.3 V

0.125

3.75 k

(10.3, 13.2, 12.5)

Pulse PAG6356.081NLT

1. Not all recommended part numbers are validated by Texas Instruments. Refer to the latest transformer

specifications to determine compatibility with SN6507-Q1.

9.3 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 3 V and 36 V nominal. If the input

supply is located more than a few inches from the device, a 0.1 μF by-pass capacitor should be connected as

close as possible to the device VCC pin and a 10 μF capacitor should be connected close to the transformer

center-tap pin.

9.4 Layout

9.4.1 Layout Guidelines

• The power supply input, VIN, must be buffered to ground with a low-ESR ceramic bypass-capacitor. The

recommended capacitor value can range from 1 μF to 10 μF, and is typically 10 μF. The capacitor must have

a voltage rating greater than the VIN voltage level and an X5R or X7R dielectric.

• The optimum placement of the VIN capacitor is closest to the VIN and GND pins at the board entrance to

minimize the loop area formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See

Figure 9-10 for a PCB layout example.

• To help ensure reliable operation, a 0.1-μF low-ESR ceramic bypass-capacitor is recommended at the device

VCC pin. The capacitor should be placed as close to the supply pins as possible in the PCB layout and on the

same layer. The capacitor must have a voltage rating greater than the VIN voltage level.

• The connections between the device SW1 and SW2 pins and the transformer primary endings and the

connection of the device VCC pin and the transformer center-tap must be as short as possible for minimum

trace inductance.

• The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a

low-ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF, and is

typically 10 μF. The capacitor must have a voltage rating greater than the VIN voltage level and an X5R or

X7R dielectric.

• The device GND pins must be tied to the PCB ground plane using two vias to help minimize inductance.

SN6507-Q1

SLLSFM1 – SEPTEMBER 2022

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