SN6507 datasheet(21/44 Pages) TI

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strength. Soft-start prevents high inrush current from VCC while charging large secondary side decoupling

capacitors, and also prevents overshoot in secondary voltage during power-up.

The sort-start time to ramp to the peak switch current is calculated by the capacitor and resistor on SS/ILIM pin

with the following formula.

TSS= CSS

275μA− 0.6RILIM

(4)

During soft-start, the over-current protection is disabled. To ensure a smooth transition between soft-start and

the steady state, it's recommended to have a CSS value between 50 nF and 5 µF with an output capacitor, COUT,

of less than 10 times the value of CSS.

8.4.2 Operation Mode

The SN6507-Q1 driver is in operation mode when EN pin is above ENUVLO, VIN pin is above VCCUVLO, and

soft-start completes. In normal operation mode, the switching frequency is fixed, determined either by the CLK

pin resistor or external Clock signal.

8.4.3 Shutdown Mode

The device has a dedicated EN/UVLO pin to put the device in very low power mode to save power when not

in use. EN/UVLO pin has an internal pull down resistor which keeps device disabled when not driven. When

disabled or when VCC is < 2.8 V , both drain outputs, SW1 and SW2, are tri-stated.

8.4.4 SYNC Mode

The SN6507-Q1 has a CLK pin which can be used to synchronize the device with system clock and in turn

with other SN6507-Q1 devices so that the system can control the exact switching frequency of the device. In

SYNC mode, the CLK frequency is divided by two to drive the gates of powerFETs. Figure 9-2 shows the timing

diagram for the same.

The device cannot automatically change from SYNC mode to switching frequency control using the internal

oscillator or resistor-programmable switching frequency mode. If a valid external CLK signal is not present, the

output will stop switching, and a power cycle will be required to change the switching mode back to using the

internal oscillator or the adjustable switching frequency using RCLK.

When the device is in SYNC mode, duty cycle control and SSM are not supported, therefore it's recommended

to leave DC pin floating in SYNC mode to reduce the solution size.

Note that it is recommended that the SN6507-Q1 VCC pin powers up before CLK pin. Before device power-up,

the initial state of external clock should be high-impedance.

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SN6507-Q1

SLLSFM1 – SEPTEMBER 2022

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SN6507 Datasheet(PDF) 21 Page - Texas Instruments