ADXL314 datasheet(12/27 Pages) AD

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Data Sheet

ADXL314

THEORY OF OPERATION

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If a single-byte read operation is performed, the remaining bytes

of data for the current FIFO sample are lost. Therefore, data for

all axes of interest must be read in a burst (multiple byte) read

operation. To ensure that the FIFO buffer is empty (that is, all new

data has moved into the data registers), an interval of at least

5 µs must elapse between the end of the read back from the

data registers and the start of a new read of the data registers

or the FIFO_STATUS register (Address 0x39). The end of a read

operation from the data registers is signified by the transition from

When SPI operation is enabled at a frequency of 1.6 MHz or

lower, the register addressing portion of the transmission provides

a sufficient delay to ensure that the FIFO buffer has completely

emptied. When SPI operation is enabled at a frequency higher than

1.6 MHz, the CS pin must be deasserted to ensure a total delay of

5 µs; otherwise, the delay is not sufficient. When SPI operation is

enabled at 5 MHz, the total delay necessary is at most 3.4 µs.

When I2C mode is enabled on the device, the communication rate

is low enough to ensure a sufficient delay between FIFO reads.

INTERRUPTS

The ADXL314 provides two output pins for driving interrupts: INT1

and INT2. Both interrupt pins are push-pull, low impedance pins

with output specifications shown in Table 11. The default configu-

ration of the interrupt pins is active high. This configuration can

be changed to active low by setting the INT_INVERT bit in the

DATA_FORMAT (Address 0x31) register. All functions can be used

simultaneously, with the only limiting feature being that some func-

tions may need to share interrupt pins.

Interrupts are enabled by setting the appropriate bit in the INT_EN-

ABLE register (Address 0x2E) and are mapped to either the INT1

or INT2 pin based on the contents of the INT_MAP register

(Address 0x2F). When initially configuring the interrupt pins, it is

recommended that the functions and interrupt mapping be done be-

fore enabling the interrupts. When changing the configuration of an

interrupt, it is recommended that the interrupt be disabled first, by

clearing the bit corresponding to that function in the INT_ENABLE

interrupt again. Configuration of the functions while the interrupts

are disabled helps to prevent the accidental generation of an

interrupt before desired.

The interrupt functions are latched and cleared by either reading

the data registers (Address 0x32 to Address 0x37) until the interrupt

condition is no longer valid for the data-related interrupts or by

reading the INT_SOURCE register (Address 0x30) for the remain-

ing interrupts. This section describes the interrupts that can be set

in the INT_ENABLE register and monitored in the INT_SOURCE

DATA_READY

The DATA_READY bit is set when new data is available and is

cleared when no new data is available.

Activity

The activity bit is set when acceleration greater than the value stor-

ed in the THRESH_ACT register (Address 0x24) is experienced.

Inactivity

The inactivity bit is set when acceleration of less than the value

stored in the THRESH_INACT register (Address 0x25) is experi-

enced for more time than is specified in the TIME_INACT register

(Address 0x26). The maximum value for TIME_INACT is 255 sec.

Watermark

The watermark bit is set when the number of samples in FIFO

equals the value stored in the samples bits (Register FIFO_CTL,

Address 0x38). The watermark bit is cleared automatically when

FIFO is read, and the content returns to a value less than the value

stored in the samples bits.

Overrun

The overrun bit is set when new data replaces unread data. The

precise operation of the overrun function depends on the FIFO

mode. In bypass mode, the overrun bit is set when new data

replaces unread data in the DATAX, DATAY, and DATAZ registers

(Address 0x32 to Address 0x37). In all other modes, the overrun bit

is set when FIFO is filled. The overrun bit is automatically cleared

when the FIFO content is read.

Table 11. Interrupt Pin Digital Output

Parameter

Test Conditions

Limit1

Unit

Min

Max

Digital Output

Low Level Output Voltage (VOL)

IOL = 300 µA

0.2 × VDD I/O

High Level Output Voltage (VOH)

IOH = −150 µA

0.8 × VDD I/O

Low Level Output Current (IOL)

VOL = VOL, max

300

µA

High Level Output Current (IOH)

VOH = VOH, min

−150

µA

Pin Capacitance

Input frequency (fIN) = 1 MHz,

input voltage (VIN) = 2.5 V

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