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Data Sheet

ADXL314

SERIAL COMMUNICATIONS

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Rev. A | 14 of 27

The ADXL314 can communicate via I2C and SPI digital communi-

cations interfaces. In both cases, the ADXL314 operates as a

subordinate. If I2C is the desired interface for the application, tie

the CS pin directly to VDD I/O as shown in Figure 26. If SPI is

the desired interface for the application, drive the CS pin with an

external controller, as demonstrated in Figure 20 and Figure 21.

Because the I2C interface is enabled any time the CS pin is brought

up to VDD I/O, there is a potential for bus conflicts to occur when

the ADXL314 is implemented into a SPI network. Refer to the

Preventing Bus Traffic Errors section for information on how to

avoid such conditions. In both SPI and I2C modes of operation,

ignore data transmitted from the ADXL314 to the controller device

during writes to the ADXL314.

Note that throughout this section, multifunction pins, such as

SDA/SDI/SDIO, are referred to either by the entire pin name or

by a single function of the pin, for example, SDA, when only that

function is relevant.

SERIAL PORT INPUT AND OUTPUT DEFAULT

STATES

Ensure that all serial port inputs and outputs are in a defined state

and that pins are not allowed to float when they are not in use.

These two conditions are applicable to all serial port inputs and

outputs, regardless of SPI or I2C operation.

For I2C applications, always tie the pin high to VDD I/O. Connect the

SCL and SDA pins to an external controller, with pull-up resistors

implemented according to the UM10204 I2C-Bus Specification and

User Manual, Rev. 03—19 June 2007, available from NXP Semi-

conductor. The ALT ADDRESS pin must be tied to either VDD I/O or

ground, thereby selecting the desired I2C address for the ADXL314.

If SPI is the intended communications interface, drive the CS pin

with an external controller, as shown in Figure 20 and Figure 21.

When communications with the ADXL314 are suspended (CS =

VDD I/O), ensure that the SCLK, SDI/SDIO, and SDO pins are not

floating.

For either SPI or I2C operation, not taking these precautions may

result in an inability to communicate with the device or excessive

current consumption.

SPI

For the SPI, either 3-wire or 4-wire configuration is possible, as

shown in the connection diagrams in Figure 20 and Figure 21.

Clearing the SPI bit in the DATA_FORMAT register (Address 0x31)

selects 4-wire mode, whereas setting the SPI bit in the DATA_FOR-

MAT register (Address 0x31) selects 3‑wire mode. The maximum

SPI clock speed is 5 MHz with 100 pF maximum loading, and the

timing scheme follows clock polarity (CPOL) = 1 and clock phase

(CPHA) = 1. If power is applied to the ADXL314 before the clock

polarity and phase of the host processor are configured, bring the

pin high before changing the clock polarity and phase.

When using 3-wire SPI, pull the SDO pin up to VDD I/O or down to

ground via a 10 kΩ resistor, as shown in Figure 20.

CS is the serial port enable line and is controlled by the SPI

controller. This line must go low at the start of a transmission and

high at the end of a transmission, as shown in Figure 23. SCLK is

the serial port clock and is supplied by the SPI controller. SDI and

SDO are the serial data input and output, respectively.

Figure 20. 3-Wire SPI Connection Diagram

Figure 21. 4-Wire SPI Connection Diagram

To read or write multiple bytes in a single transmission, the multiple

byte bit, located after the R/W bit in the first byte transfer (MB in

Figure 23 to Figure 25), must be set. After the register addressing

and the first byte of data, each subsequent set of clock pulses

(eight clock pulses) causes the ADXL314 to point to the next

pulses cease and CS is deasserted. To perform reads or writes on

different nonsequential registers, CS must be deasserted between

transmissions, and the new register must be addressed separately.

The timing diagram for 3-wire SPI reads or writes is shown in Fig-

ure 25. The 4-wire equivalents for SPI writes and reads are shown

in Figure 23 and Figure 24, respectively. For correct operation of

the device, the logic thresholds and timing parameters in Table 12

and Table 13 must be met at all times.

Use of the 3200 Hz and 1600 Hz output data rates is only recom-

mended with SPI communication rates greater than or equal to

2 MHz. The 800 Hz output data rate is recommended only for

communication speeds greater than or equal to 400 kHz, and

the remaining data rates scale proportionally. For example, the

minimum recommended communication speed for a 200 Hz output

data rate is 100 kHz. Operation at an output data rate less than

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