ADXL314 datasheet(21/27 Pages) AD

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Data Sheet

ADXL314

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disables automatic switching to sleep mode. See the description of

the sleep bit in the Sleep Bit section for more information.

When clearing the AUTO_SLEEP bit, it is recommended that the

device be placed into standby mode and then set back to meas-

urement mode with a subsequent write. This recommendation is

advised to ensure that the device is properly biased if sleep mode is

manually disabled. Otherwise, the first few samples of data after the

AUTO_SLEEP bit is cleared may have additional noise, especially if

the device was asleep when the bit was cleared.

Measure Bit

A setting of 0 in the measure bit places the device into standby

mode, and a setting of 1 places the device into measurement

mode. The ADXL314 powers up in standby mode with minimum

power consumption.

Sleep Bit

A setting of 0 in the sleep bit puts the device into the normal

mode of operation, and a setting of 1 places the device into sleep

mode. Sleep mode suppresses DATA_READY (see Register 0x2E,

FIFO, and switches the sampling rate to one specified by the

wake-up bits. In sleep mode, only the activity function can be used.

When clearing the sleep bit, it is recommended that the device

be placed into standby mode and then set back to measurement

mode with a subsequent write. This recommendation is advised to

ensure that the device is properly biased if sleep mode is manually

disabled. Otherwise, the first few samples of data after the sleep bit

is cleared may have additional noise, especially if the device was

asleep when the bit was cleared.

Wake-Up Bits

These bits control the frequency of readings in sleep mode as

described in Table 22.

Table 22. Frequency of Readings in Sleep Mode

Setting

Frequency (Hz)

Table 23. Register 0x2E—Bits[D7:D4]

DATA_READY

Not applicable

Activity

Table 24. Register 0x2E—Bits[D3:D0]

Inactivity

Not applicable

Watermark

Overrun

Setting bits in this register to 1 enables their respective functions

to generate interrupts, whereas setting bits in this register to 0 pre-

vents the functions from generating interrupts. The DATA_READY,

watermark, and overrun bits enable only the interrupt output; the

functions are always enabled. It is recommended that interrupts be

configured before enabling their outputs.

Table 25. Register 0x2F—Bits[D7:D4]

DATA_READY

Not applicable

Activity

Table 26. Register 0x2F—Bits[D3:D0]

Inactivity

Not applicable

Watermark

Overrun

Any bits set to 0 in this register send their respective interrupts

to the INT1 pin, whereas bits set to 1 in this register send their

respective interrupts to the INT2 pin. All selected interrupts for a

given pin are OR’ed.

Table 27. Register 0x30—Bits[D7:D4]

DATA_READY

Not applicable

Activity

Table 28. Register 0x30—Bits[D3:D0]

Inactivity

Not applicable

Watermark

Overrun

Bits set to 1 in this register indicate that their respective functions

have triggered an event, whereas bits set to 0 indicate that the cor-

responding event has not occurred. The DATA_READY, watermark,

and overrun bits are always set if the corresponding events occur,

regardless of the INT_ENABLE register settings, and are cleared by

reading data from the DATAX, DATAY, and DATAZ registers. Other

bits, and the corresponding interrupts, are cleared by reading the

INT_SOURCE register.

Table 29. Register 0x31

SELF_TEST SPI INT_INVERT

Justify

The DATA_FORMAT register controls the presentation of data to

SELF_TEST Bit

A setting of 1 in the SELF_TEST bit applies a self test force to the

sensor, causing a shift in the output data. A value of 0 disables the

self test force. For more information about the self test function, see

the Self Test section and the Using Self Test section.

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