ADXL314 datasheet(22/27 Pages) AD

22 / 27 page

Data Sheet

ADXL314

analog.com

Rev. A | 22 of 27

SPI Bit

Set the SPI bit to 1 to set the device to 3-wire SPI mode, and set

the SPI bit to 0 to set the device to 4-wire SPI mode.

INT_INVERT Bit

Set the INT_INVERT bit to 1 to set the interrupts to active high, and

set the INT_INET bit to 1 to set the interrupts to active low.

Justify Bit

A setting of 1 in the justify bit selects left (MSB) justified mode, and

a setting of 0 in the justify bit selects right justified mode with a sign

extension.

DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1

(Read Only)

These six bytes (Register 0x32 to Register 0x37) are eight bits

each and hold the output data for each axis. Register 0x32 and

and Register 0x37 hold the output data for the z-axis.

The output data is twos complement, with DATAx0 as the least

significant byte, and DATAx1 as the most significant byte, where x

represent X, Y, or Z. The DATA_FORMAT register (Address 0x31)

controls the format of the data. It is recommended that a multiple-

byte read of all registers be performed to prevent a change in data

between reads of sequential registers.

Table 30. Register 0x38

FIFO_MODE

Trigger

Samples

FIFO_MODE Bits

The FIFO_MODE bits set the FIFO mode, as described in Table 31.

Table 31. FIFO Modes

Setting

Mode

Function

Bypass

The FIFO buffer is bypassed.

FIFO

The FIFO buffer collects up to 32 values and then

stops collecting data. The FIFO buffer only collects

new data when the FIFO buffer is not full.

Stream

The FIFO buffer holds the last 32 data values. When

the FIFO buffer is full, the oldest data is overwritten

with newer data.

Trigger

When triggered by the trigger bit, the FIFO buffer

holds the last data samples before the trigger event

and then continues to collect data until full. New data

is collected only when the FIFO buffer is not full.

Trigger Bit

A value of 0 in the trigger bit links the trigger event of trigger mode

to INT1, and a value of 1 in the trigger bit links the trigger event to

INT2.

Samples Bits

The function of the samples bits depends on the FIFO mode

selected (see Table 32). Entering a value of 0 in the samples bits

immediately sets the watermark status bit in the INT_SOURCE

operation may occur if a value of 0 is used for the samples bits

when trigger mode is used.

Table 32. Samples Bits Functions

FIFO Mode

Samples Bits Function

Bypass

None.

FIFO

Specifies how many FIFO entries are needed to trigger a

watermark interrupt.

Stream

Specifies how many FIFO entries are needed to trigger a

watermark interrupt.

Trigger

Specifies how many FIFO samples are retained in the FIFO

buffer before a trigger event.

Table 33. Register 0x39

FIFO_TRIG

Entries

FIFO_TRIG Bit

A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring,

and a 0 means that a FIFO trigger event has not occurred.

Entries Bits

The entries bits report how many data values are stored in the

FIFO. Access to collect the data from the FIFO is provided through

the DATAX, DATAY, and DATAZ registers. The FIFO reads must be

done in burst or multiple-byte mode because each FIFO level is

cleared after any read (single- or multiple-byte) of the FIFO. The

FIFO stores a maximum of 32 entries, which equates to a maximum

of 33 entries available at any given time because an additional

entry is available at the output filter of the device.

ADXL314 Datasheet(PDF) 22 Page - Analog Devices

ADXL314 Datasheet(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Datasheet Download

Link URL