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ADXL314 Datasheet(PDF) 24 Page - Analog Devices

Part # ADXL314
Description  ±200 g Range, 3-Axis Digital Accelerometer
PDF  27 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADXL314 Datasheet(HTML) 24 Page - Analog Devices

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Data Sheet
ADXL314
APPLICATIONS INFORMATION
analog.com
Rev. A | 24 of 27
OFFSET COMPENSATION
Accelerometers are mechanical structures containing elements that
are free to move. These moving parts can be sensitive to mechani-
cal stresses, much more so than solid state electronics.
The 0 g bias, or offset, is an important accelerometer metric be-
cause it defines the baseline for measuring acceleration. Additional
stresses can be applied during assembly of a system containing
an accelerometer. These stresses can come from, but are not
limited to, component soldering, board stress during mounting, and
application of any compounds on or over the component. If offset
compensation is deemed necessary, it is recommended that it be
performed after system assembly.
USING SELF TEST
The self test change is defined as the difference between the
acceleration output of an axis with self test enabled and the
acceleration output of the same axis with self test disabled. Due
to device filtering, the output reaches its final value after 4 × τ
when enabling or disabling self test, where τ = 1/(data rate). This
definition assumes that the sensor does not move between these
two measurements; if the sensor moves, a nonself test related shift
corrupts the test.
The self test response in all axes exhibits bimodal behavior. Howev-
er, performing the self test check in the z-axis is a reliable way to
corroborate the integrity of the sensor.
Proper configuration of the ADXL314 is necessary for an accurate
self test measurement. To configure the device for self test, take the
following steps:
1. Set the data rate from 100 Hz to 800 Hz, or set the data
rate to 3200 Hz by writing to the rate bits (Bits[D3:D0]) in the
BW_RATE register (Address 0x2C). Write a value from 0x0A to
0x0D, or write 0x0F to the BW_RATE register.
2. Configure the device for normal power operation by clearing the
LOW_POWER bit (Bit D4) in the BW_RATE register (Address
0x2C).
3. Retrieve samples of z-axis acceleration data from the sensor
and average them together. Averaging at least 10 samples is
recommended.
4. Store the averaged value and label it as ZST_OFF.
5. Enable self test by setting the SELF_TEST bit (Bit D7) in the
DATA_FORMAT register (Address 0x31). Note that the output
requires approximately four samples to settle after self test is
enabled.
6. Retrieve samples of z-axis acceleration data and average them
together. Averaging at least 10 samples is recommended.
7. Store the averaged value and label it as ZST_ON.
8. Disable self test by clearing the SELF_TEST bit (Bit D7) in the
DATA_FORMAT register (Address 0x31).
With the stored value for self test enabled and disabled, the self test
change is as follows:
ZST = ZST_ON − ZST_OFF
This value can be converted to g by multiplying by the
48.83 mg/LSB scale factor.
If the self test change is within the valid range, the test is consid-
ered successful. Generally, a device is considered to pass if the
minimum magnitude of change is achieved. However, a device that
changes by more than the maximum magnitude is not necessarily a
failure.
Another effective method for using the self test to verify that
accelerometer functionality is to toggle the self test at a certain
rate and then perform an FFT on the output. The FFT must have
a corresponding tone at the frequency where the self test was
toggled. Using an FFT in this way removes the dependency of the
test on supply voltage and self test magnitude, which can vary
within a rather wide range.
ASYNCHRONOUS DATA READINGS
Asynchronous readings of acceleration data can lead to accessing
the acceleration data registers while they are being updated. To
avoid this, it is recommended to either enable FIFO stream mode or
to synchronize a SPI/I2C transaction to the DATA_READY interrupt
functionality, so that the host processor samples immediately after
the DATA_READY interrupt goes high.
DATA FORMATTING AT OUTPUT DATA RATE
OF 3200 HZ AND 1600 HZ
When using the 3200 Hz or 1600 Hz output data rate, the LSB of
the output data-word is always 0. When the data is right justified,
the LSB corresponds to Bit D0 of the DATAx0 register, and when
the data is left justified, the LSB corresponds to Bit D3 of the
DATAx0 register.



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