S12ECT16B8CV2 datasheet(112/152 Pages) NXP

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MC9S12XDP512 Device User Guide — V01.12

A.1.6 ESD Protection and Latch-up Immunity

All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade

Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body

Model (HBM), the Machine Model (MM) and the Charge Device Model.

A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification. Complete DC parametric and functional testing is performed per the applicable device

specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.

2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.

The absolute maximum ratings apply when the device is powered from an external source.

3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.

4. Those pins are internally clamped to VSSPLL and VDDPLL.

5. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.

Table A-2 ESD and Latch-up Test Conditions

Model

Description

Symbol

Value

Unit

Human Body

Series Resistance

1500

Ohm

Storage Capacitance

100

Number of Pulse per pin

positive

negative

Machine

Series Resistance

Ohm

Storage Capacitance

200

Number of Pulse per pin

positive

negative

Latch-up

Minimum input voltage limit

-2.5

Maximum input voltage limit

7.5

Table A-3 ESD and Latch-Up Protection Characteristics

Num C

Rating

Symbol

Min

Max

Unit

C Human Body Model (HBM)

VHBM

2000

C Machine Model (MM)

VMM

200

C Charge Device Model (CDM)

VCDM

500

Latch-up Current at TA = 125°C

positive

negative

ILAT

+100

-100

-mA

Latch-up Current at TA = 27°C

positive

negative

ILAT

+200

-200

-mA

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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