M66596 datasheet(86/133 Pages) RENESAS

86 / 133 page

M66596FP/WG

rev .1.00

2006.3.14

page 84 of 127

3.4.3.6 BRDY interrupt timing selection function

By setting the BFRE bit of the PIPECFG register, it is possible to keep the BRDY interrupt from being

generated when a data packet consisting of the maximum packet size is received.

When using DMA transfers, this function can be used to generate an interrupt only when the last data item

has been received. The “last data item” refers to the reception of a short packet, or the ending of the transaction

counter. When a short packet has been received, the BRDY interrupt is generated after the received data has

been read. When the BRDY interrupt is generated, the length of the data received in the last data packet to have

been received can be confirmed.

Table 3.21 shows the timing at which the BRDY interrupts are generated by the controller.

Table 3.21Timing at which BRDY interrupts are generated

Buffer state when packet is received

BFRE = “0”

BFRE = “1”

Buffer full

When packet is

received

Not generated

Zero-Length packet received

When packet is

received

When packet is received

Normal packet received

When packet is

received

When reading of the received data from

the buffer memory has been completed

Transaction counter ended

When packet is

received

When reading of the received data from

the buffer memory has been completed

This function is valid only in the direction of reading from the buffer memory. In the writing direction, the BFRE bit

should be fixed at “0”.

3.4.4

Timing at which the FIFO port can be accessed

This chapter explains the access timing to FIFO port. When there is no description, both a Host and Peripheral are

the same operation.

3.4.4.1 Timing at which the FIFO port can be accessed when switching pipes

Figure 3.23 shows a diagram of the timing up to the point where the FRDY bit and DTLN bit are determined when

the pipe specified by the FIFO port has been switched (the CURPIPE bit of the C/DxFIFOSEL register has been

changed).

If the CURPIPE bit has been changed, access to the FIFO port should be carried out after waiting 450 ns after

writing to the C/DxFIFOSEL register.

The same timing applies with respect to the CFIFO port, when the ISEL bit is changed.

Indefinite

WR N

CURPIPE

FRDY

DTLN

max 450ns

max 100ns

min 20ns

PIPE-A

PIPE-B

Writing of the CURPIPE bit

Figure 3.23 Timing at which the FRDY and DTLN bits are determined after changing a pipe

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