TMPR4925 datasheet(344/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-82

10.4.54 G2P Configuration Data Register (G2PCFGDATA)

0xD1A4

This is the only register that supports Byte access and 16-bit Word access. The upper address bit of

the PCI Configuration Space is specified by the G2P Configuration Address Register (G2PCFGADRS).

The lower two bits of the address are specified by the lower two bits of the offset address in this register

as shown in Table 10.4.2. The TX4925 also has the ability to swap Byte Enables for Configuration

Cycles by setting G2PCFG.BSWAPI.

Table 10.4.2 PCI Configuration Space Access Address

Offset Address

Access Size

Configuration Space

Address [1:0]

Little Endian Mode

Big Endian Mode

32-bit

0xD1A4

0xD1A6

16-bit

0xD1A6

0xD1A4

0xD1A7

0xD1A5

0xD1A6

0xD1A5

8-bit

0xD1A7

0xD1A4

ICD

R/W

: Type



: Initial value

ICD

R/W

: Type



: Initial value

Bits

Mnemonic

Field Name

Description

31:0

ICD

Initiator

Configuration

Data

Initiator Configuration Data Register (Initial value: R/W)

This is a data port that is used when performing initiator PCI configuration access.

PCI configuration Read or Write transactions are issued when this register is read to

or written from.

Figure 10.4.54 G2P Configuration Data Register

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