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TMPR4925 Datasheet(PDF) 362 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 362 Page - Toshiba Semiconductor |
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362 / 590 page ![]() Chapter 10 PCI Controller 10-100 10.5.3 Power Management Capability Register (PMC) 0xDE 15 11 10 9 8 6 5 4 3 2 0 PMESPT D2SPT D1SPT Reserved DSI Reserved PMECLK PMVER R R R RRR : Type 0x00 0 0 0 0 0x2 : Initial value Bits Mnemonic Field Name Description 15:11 PMESPT PME Output Support PME_ Support (Fixed value: 0x00, R) On TX4925 the function is not supported. 10 D2SPT D2 Support D2_Support (Fixed value: 0, R) 0: Indicates that the D2 state is not supported. 9 D1SPT D1 Support D1_Support (Fixed value: 0, R) 0: Indicates that the D1 state is not supported. 8:6 Reserved 5 DSI DSI DSI (Fixed value: 0, R) 1: Indicates that Device Specific Initialization is required. 4 Reserved 3 PMECLK PME Clock PME Clock (Fixed value: 0, R) 0: Indicates that the PCI Clock is not required to assert the PME* signal. 2:0 PMVER Power Management I/F Version Version (Fixed value: 0x2, R) 2: Indicates compliance with “PCI Power Management Interface Specification” Version 1.1. Figure 10.5.3 Power Management Capability Register |
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