TMPR4925 datasheet(173/590 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-3

8.3

Detailed Explanation

8.3.1

Transfer Mode

The DMA Controller supports five transfer mode types (refer to Table 8.3.1 below). The setting of

the External Request bit (DMCCRn.EXTRQ) of the DMA Channel Control Register selects whether

transfer with an I/O device is a DMA transfer.

•

I/O DMA Transfer Mode (DMCCRn.EXTRQ = “1”)

Perform DMA transfer with either an external device connected to the External Bus Controller or

an on-chip I/O device (ACLC or SIO).

•

Memory Transfer Mode (DMCCRn.EXTRQ = “0”)

Either copies data between memory devices or fills data in memory.

Table 8.3.1 DMA Controller Transfer Modes

Transfer Mode

DMCCRn

EXTREQ

DRQCTR

DMAREQn

DMCCRn

SNGAD

DMSAR

DMDAR

Ref.

External I/O

(Single Address)

0xxxx

√

8.3.3

8.3.7

External I/O

(Dual Address)

0xxxx

√√

8.3.3

8.3.8

Internal I/O

10xx (SIO)

11xx (ACLC)

√√

8.3.4

8.3.8

Memory-Memory Copy

√√

8.3.4

8.3.8

Fill Memory

√

8.3.6

8.3.7

8.3.2

On-chip Registers

The DMA Controller has two shared registers that are shared by four channels. Section 8.4 explains

each register in detail.

•

Shared Registers

DMMCR:

DMA Master Control Register

DMMFDR:

DMA Memory Fill Data Register

•

DMA Channel Register

DMCHARn:

DMA Chained Address Register

DMSARn:

DMA Source Address Register

DMDARn:

DMA Destination Address Register

DMCNTRn:

DMA Count Register

DMSAIRn:

DMA Source Address Increment Register

DMDAIRn:

DMA Destination Address Increment Register

DMCCRn:

DMA Channel Control Register

DMCSRn:

DMA Channel Status Register

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