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ES9033 Datasheet(PDF) 25 Page - ESS Technology,Inc |
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ES9033 Datasheet(HTML) 25 Page - ESS Technology,Inc |
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25 / 103 page ![]() 0.3.1 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 ES9033 Datasheet Information 25 Clock Distribution The ES9033 includes features for selecting and manipulating the input clock source. System Clock (MCLK) Reg 193[7] SCL_SLAVE I2C/SPI Clock BCK EN Reg 0[2] CLK DIV Reg 2[5:0] DAC Interpolation Path Clock (128fs clock) Reg 3[6:0] Reg 37 Reg 38[6:4] Master BCK Master WS Enable Reg 193[0] Reg 193[1] DATA1 WS Reg 1[1] DSD Clock Reg 1[0] TDM Clock Digital DAC Analog DAC Clock Analog DAC PLL Reg 0[3] CLK NSMOD Noise Shaped Modulator EN CLK DIV EN TDM Decoder DSD Decoder EN Master BCK/WS Gen Reg 0[5:4] DoP Decoder DoP Clock Reg 1[2] MCLK DATA_CLK EN DIV4 EN Figure 7 - ES9033 Clock Distribution |
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