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ES9033 Datasheet(PDF) 48 Page - ESS Technology,Inc |
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ES9033 Datasheet(HTML) 48 Page - ESS Technology,Inc |
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48 / 103 page  a 0.3.1 ES9033 Datasheet Information ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 48 Register 3: MASTER CLOCK CONFIG Bits [7] [6:0] Default 1’b0 7’d7 Bits Mnemonic Description [7] SELECT_MENC_HALF Master Encoder (MENC) • 1’b0: Divide by SELECT_MENC_NUM + 1 (default) • 1’b1: Divide by half of SELECT_MENC_NUM + 1 Note: Can only produce half of an odd number divide [6:0] SELECT_MENC_NUM Master mode clock divider. Whole number divide value + 1 for CLK_Master (SYS_CLK/divide_value). • 7’d0: Whole number divide value + 1 = 1 • 7’d1: Whole number divide value + 1 = 2 • 7’d127: Whole number divide value + 1 = 128 Register 4: CP CLOCK DIV Bits [7:0] Default 8’d31 Bits Mnemonic Description [7:0] CP_CLK_DIV Specifies the clk divider for the CP clock source. Valid from 8’d0 to 8’d255. 8’dX: CP clock is SYS_CLK/((X+1)*2) • 8’d0: Minimum • 8’d31: Defaults • 8’d255: Maximum Register 8-5: RESERVED |
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