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ES9033 Datasheet(PDF) 44 Page - ESS Technology,Inc

Part # ES9033
Description  32-bit High-Performance 2-Channel DAC with Line Drivers
PDF  103 Pages
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Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9033 Datasheet(HTML) 44 Page - ESS Technology,Inc

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ES9033 Datasheet Information
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM
44
0x29
41
RESERVED
RESERVED
0x2A
42
TDM SLOT CONFIG
TDM_CH2_SLOT_SEL
TDM_CH1_SLOT_SEL
0x2B
43
RESERVED
RESERVED
0x2C
44
RESYNC CONFIG
RESERVED
CP_PDB_ON
_MUTE
RESERVED
0x2D
45
DSD 2DB DOWN
DSD_2DB_D
OWN
RESERVED
0x2E
46
VOLUME1
VOLUME1
0x2F
47
VOLUME2
VOLUME2
0x30
48
DAC VOL UP RATE
DAC_VOL_RATE_UP
0x31
49
DAC VOL DOWN RATE
DAC_VOL_RATE_DOWN
0x32
50
DAC VOL DOWN RATE FAST
DAC_VOL_RATE_FAST
0x33
51
MUTE CTRL
FORCE_VOL
UME
DAC_USE_M
ONO_VOLU
ME
RUN_VOLU
ME
RESERVED
DAC_INVERT
_CH2
DAC_INVERT_
CH1
DAC_MUTE
_CH2
DAC_MUTE_
CH1
0x34
52
FILTER CONFIG
AUTO_CH_D
ETECT
BYPASS_DEE
MPH
PEAK_FILTER
SEL_DEEMPH
FILTER_SHAPE
0x35
53
RESERVED
RESERVED
0x36
54
DATAPATH CONTROL
RESERVED
BYPASS_FIR
4X
BYPASS_FIR
2X
0x37
55
THD COMP C2 CH1
THD_C2_CH1
0x38
56
THD COMP C2 CH1
THD_C2_CH1
0x39
57
THD COMP C3 CH1
THD_C3_CH1
0x3A
58
THD COMP C3 CH1
THD_C3_CH1
0x3B
59
THD COMP C2 CH2
THD_C2_CH2
0x3C
60
THD COMP C2 CH2
THD_C2_CH2
0x3D
61
THD COMP C3 CH2
THD_C3_CH2
0x3E
62
THD COMP C3 CH2
THD_C3_CH2
0x3F
63
AUTOMUTE TIME
AUTOMUTE_TIME
0x40
64
AUTOMUTE TIME
AUTOMUTE
_RAMP_TO_
GROUND
AUTOMUTE
_WAIT_ON_
DRE
RESERVED
AUTOMUTE
_EN_CH2
AUTOMUTE
_EN_CH1
AUTOMUTE_TIME
0x41
65
AUTOMUTE LEVEL
AUTOMUTE_LEVEL
0x42
66
AUTOMUTE LEVEL
AUTOMUTE_LEVEL
0x43
67
AUTOMUTE OFF LEVEL
AUTOMUTE_OFF_LEVEL
0x44
68
AUTOMUTE OFF LEVEL
AUTOMUTE_OFF_LEVEL
0x45
69
SOFT RAMP CONFIG
GAIN_18DB_
CH2
GAIN_18DB_
CH1
SOFT_RAMP
_TYPE
SOFT_RAMP_TIME
0x46
70
RESERVED
RESERVED
0x47
71
RESERVED
RESERVED
0x48
72
RESERVED
RESERVED
0x49
73
DRE FORCE
DRE_FORCE
_CH2
DRE_FORCE
_CH1
RESERVED
0x4A
74
DRE GAIN CH1
DRE_GAIN1
0x4B
75
DRE GAIN CH1
DRE_GAIN1
0x4C
76
DRE GAIN CH2
DRE_GAIN2
0x4D
77
DRE GAIN CH2
DRE_GAIN2
0x4E
78
DRE ON THRESHOLD
DRE_ON_THRESH
0x4F
79
DRE ON THRESHOLD
DRE_ON_THRESH
0x50
80
DRE OFF THRESHOLD
DRE_OFF_THRESH
0x51
81
DRE OFF THRESHOLD
DRE_OFF_THRESH
0x52
82
DRE DECAY RATE
DRE_FORCE
_LEVEL
RESERVED
MIN_PEAK
DRE_DECAY_RATE
0x53
83
DC OFFSET CH1
DC_OFFSET1
0x54
84
DC OFFSET CH1
DC_OFFSET1
0x55
85
DC OFFSET CH2
DC_OFFSET2
0x56
86
DC OFFSET CH2
DC_OFFSET2
0x57
87
DC RAMP RATE
DC_RAMP_RATE
0x58
88
MASTER TRIM
MASTER_TRIM
0xC0
192
RESET & PLL REGISTER1
AO_SOFT_R
ESET
PLL_SOFT_R
ESET
PLL_VCO_CMP_ISET
RESERVED
GPIO1_SDB
_AO
PLL_CLKHV_
PHASE
0xC1
193
PLL REGISTER2
PLL_BYP
DVDD_SHUN
TB
SEL_1V_DRE
G
PLL_HVREG_VREF_SEL
SEL_PLL_IN
EN_PLL_CLKI
N
0xC2
194
PLL REGISTER3
RESERVED
RESERVED
AUTO_LOCK_
EN
VREF_HOL
D_REG
VREF_HOLD
_ENABLE
0xC3
195
PLL REGISTER4
PLL_CP_BIAS_SEL
PLL_PFD_DELAY_SEL
PLL_VCO_FLI
MIT_PD
PLL_VCO_P
DB
PLL_CP_PDB
0xC4
196
PLL REGISTER5
PLL_VCO_BAND_CTRL
PLL_VCO_KVCO_CTRL
PLL_VCO_IB_AMP_CTRL
0xC5
197
PLL REGISTER6
PLL_CLK_FB_DIV
0xC6
198
PLL REGISTER6
PLL_CLK_FB_DIV
0xC7
199
PLL REGISTER6
PLL_CLK_FB_DIV
0xC8
200
PLL REGISTER7
PLL_FB_DIV_LOAD
PLL_FB_DIV_LOAD
0xC9
201
PLL REGISTER7
PLL_CLK_OUT_DIV_PHASE
PLL_CLK_OUT_DIV
PLL_CLK_IN_DIV
0xCA
202
PLL REGISTER7
PLL_REG_PD
B_HV
PLL_REG_PD
B_1V2
PLL_REG_BY
P_HV
PLL_REG_BY
P_1V2
PLL_LOW_B
W
PLL_CLK_OUT
_DIV_PHASE_
EN
PLL_CLK_OUT_DIV_PHASE
0xCB
203
PLL REGISTER8
PLL_VCO_FLIMIT_CTRL
PLL_DIG_RS
TB
PLL_VCO_DI
ODE_EN
RESERVED
0xE0
224
SYS READ
RESERVED
MODES
ADDR1
ADDR0
RESERVED



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