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ES9033 Datasheet(PDF) 64 Page - ESS Technology,Inc

Part # ES9033
Description  32-bit High-Performance 2-Channel DAC with Line Drivers
PDF  103 Pages
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Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9033 Datasheet(HTML) 64 Page - ESS Technology,Inc

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ES9033 Datasheet Information
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM
64
Register 38: TDM CONFIG1
Bits
[7]
[6:4]
[3:0]
Default
1’b0
3’d0
4’d1
Bits
Mnemonic
Description
[7]
TDM_RESYNC
Force TDM decoder to resynchronize (RESYNC)
•
1’b0: Let decoder sync (default)
•
1’b1: Force decoder not sync
[6:4]
MASTER_WS_SCALE
In TDM master mode, tunes master BCK/WS ratio by scaling
master WS. It allows more TDM slots in a fixed frame.
•
3’d0: No scale (default)
•
3’d1: Scale down WS by 2
•
3’d2: Scale down WS by 4
•
3’d3: Scale down WS by 8
•
3’d4: Scale down WS by 16
•
others: Reserved
[3:0]
TDM_CH_NUM
Total TDM slot number per frame = TDM_CH_NUM + 1.
•
4’d0: Minimum
•
4’d1: Default
•
4’d15: Maximum
Register 39: TDM CONFIG2
Bits
[7]
[6]
[5:0]
Default
1’b0
1’b0
6’d1
Bits
Mnemonic
Description
[7]
TDM_LJ_MODE
TDM LJ mode.
•
1’b0: Standard I2S (default)
•
1’b1: LJ mode
[6]
TDM_VALID_EDGE
TDM WS valid edge.
•
1’b0: negative edge (default)
•
1’b1: positive edge
[5:0]
TDM_VALID_PULSE_LEN
Data valid pulse length adjustment.
•
6’d1: Default



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