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ES9033 Datasheet(PDF) 82 Page - ESS Technology,Inc |
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ES9033 Datasheet(HTML) 82 Page - ESS Technology,Inc |
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82 / 103 page  a 0.3.1 ES9033 Datasheet Information ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 82 Register 193: PLL REGISTER2 Bits [7] [6] [5] [4:2] [1] [0] Default 1’b0 1’b0 1’b0 2’d0 1’d0 1’b0 Bits Mnemonic Description [7] PLL_BYP PLL bypass mode. • 1’b0: Disabled (default) • 1’b1: Enabled [6] DVDD_SHUNTB Enables digital regulator output shunt to ground (10k). Active low. • 1’b0: Enabled (default) • 1’b1: Disabled [5] SEL_1V_DREG Sets digital regulator output voltage to 1V • 1’b0: Disabled (default) • 1’b1: Enabled [4:2] PLL_HVREG_VREF_SEL PLL HVREG reference voltage selection • 3’b001: 1.6V (optimum setting, normal operation) • others: Reserved [1] SEL_PLL_IN Selects PLL input clock sources. • 1’d0: MCLK (default) • 1’d1: BCK [0] EN_PLL_CLKIN Controls PLL input clocks. • 1’b0: Disables PLL input clocks (default) • 1’b1: Enables PLL input clocks |
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