ES9033 datasheet(81/103 Pages) ESS

81 / 103 page

0.3.1

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800

ES9033 Datasheet Information

PLL Registers

Note: some registers have an implied value that is recommended for normal and optimized operation.

Bits

[7]

[6]

[5:3]

[2]

[1]

[0]

Default

1’b0

3’d0

1’b0

1’b1

Bits

Mnemonic

Description

[7]

AO_SOFT_RESET

Performs soft reset to Slave Registers.

•

1’b0: Disabled (default)

•

1’b1: Enabled

[6]

PLL_SOFT_RESET

Performs soft reset to Synchronous Slave Registers.

•

1’b0: Disabled (default)

•

1’b1: Enabled

[5:3]

PLL_VCO_I

Set Current in PLL VCO

•

Must set to 3’b110, for normal operation

[2]

RESERVED

[1]

GPIO1_SDB_SYNC

Configures GPIO1 SDB (Shutdown_b). When SYS_CLK is

provided through GPIO1, set this bit to ‘1’ to allow SYS_CLK

input.

•

1’b0: Disabled (default)

•

1’b1: Enabled

[0]

PLL_CLKHV_PHASE

Digital/analog DAC clock phase control.

•

1’b0: Digital/analog DAC clocks have inverted phase

•

1’b1: Digital/analog DAC clocks have the same phase

(default)

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