ES9033 datasheet(63/103 Pages) ESS

63 / 103 page

0.3.1

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800

ES9033 Datasheet Information

Bits

[7]

[6]

[5]

[4:3]

[2]

[1]

[0]

Default

1’b0

2’d0

1’b0

1’b1

Bits

Mnemonic

Description

[7]

AUTO_FS_DETECT_BLOCK_2XMODE

Automatic 2x mode enable.

•

1’b0: Set 2x mode when the detected

CLK_DAC/CLK_IDAC ratio is 64 (default)

•

1’b1: Do not set 2x mode when the detected

CLK_DAC/CLK_IDAC ratio is 64

[6]

MASTER_BCK_DIV1

When enabled, master BCK is 128fs clock. Otherwise, BCK is

less than or equal to 64fs.

•

1’b0: BCK is not 128fs clock (default)

•

1’b1: BCK is 128fs clock

[5]

MASTER_WS_IDLE

Sets the value of master WS when WS is idle.

•

1’b0: WS is 0 when idle (default)

•

1’b1: WS is 1 when idle

[4:3]

MASTER_FRAME_LENGTH

Selects the bit length in each TDM channel in master mode.

•

2’d0: 32 bit (default)

•

2’d2: 16 bit

•

others: Reserved

[2]

MASTER_WS_PULSE_MODE

When enabled, master WS is a pulse signal instead of a 50%

duty cycle signal. The pulse width is 1 BCK cycle.

•

1’b0: 50% duty cycle WS signal (default)

•

1’b1: Pulse WS signal

[1]

MASTER_WS_INVERT

Inverts master WS.

•

1’b0: Non-inverted (default)

•

1’b1: Inverted

[0]

MASTER_BCK_INVERT

Inverts master BCK or DSD_CLK.

•

1’b0: Non-inverted

•

1’b1: Inverted (default)

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