ES9033 datasheet(66/103 Pages) ESS

66 / 103 page

0.3.1

ES9033 Datasheet Information

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

Bits

[7]

[6]

[5:0]

Default

1’b0

1’b1

6’b000000

Bits

Mnemonic

Description

[7]

RESERVED

[6]

CP_PDB_ON_MUTE

Charge pump state control when mute

•

1’b0: Keep charge pump on when mute

•

1’b1: Turn off charge pump when mute (default)

[5]

RESERVED

[4]

SYNC_DAC_CLK_DIV

Controls clock divider reset on negative edge of WS.

•

1’b1: Clock divider will be reset at every negative edge

of WS

•

1’b0: Disable the FIR_RESYNC reset

Note: If reset the SYNC_DAC_CLK_DIV (ie 1’b1), toggle this

bit before setting any other RESYNC bits [3:0]

[3]

DOP_CLK_RESYNC

Controls DoP clock divider reset on negative edge of WS.

•

1’b1: Clock divider will be reset at every negative edge

of WS

•

1’b0: Disable the FIR_RESYNC reset

[2]

VOL_THD_RESYNC

Controls Volume-THD block reset on negative edge of WS.

•

1’b1: DoP clock generator will be reset at every

negative edge of WS

•

1’b0: Disable the DOP_CLK_RESYNC reset

[1]

FIR_RESYNC

Controls FIR filters reset on negative edge of WS.

•

1’b1: FIR filters will be reset at every negative edge of

•

1’b0: Disable the FIR_RESYNC reset

[0]

FS_RESYNC

Controls FS clock generator reset on negative edge of WS.

•

1’b1: FS clock generator will be reset at every

negative edge of WS

•

1’b0: Disable the FS_RESYNC reset

Bits

[7]

[6:0]

Default

1’b1

7’d64

Bits

Mnemonic

Description

[7]

DSD_2DB_DOWN

Scales down DSD data by 2dB to match PCM data.

•

1’b1: Scale (default)

•

1’b0: No scale

Note: DSD_2DB_DOWN requires RUN_VOLUME to be

toggled in order to take effect.

ES9033 Datasheet(PDF) 66 Page - ESS Technology,Inc

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