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ES9033 Datasheet(PDF) 8 Page - ESS Technology,Inc |
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ES9033 Datasheet(HTML) 8 Page - ESS Technology,Inc |
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8 / 103 page  a 0.3.1 ES9033 Datasheet Information ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 8 28 QFN Pin Descriptions Pin Name Pin Type Reset State Pin Description 1 AVDD Power Power 3.3V I/O supply 2 CHIP_EN I/O HiZ Active-high chip enable. 3 MODE I/O HiZ Control for SPI/I2C/HW modes 4 VCCA Power Power Analog Supply 5 DGND Ground Ground Digital ground 6 OUT1 AO Ground Output channel 1 7 GND_SNS AI Ground Line driver load ground voltage sense 8 OUT2 AO Ground Output channel 2 9 AVCC_3V3 Power Power Analog Regulator 3.3V Supply 10 AVCC Power Power Analog Regulator Output, internally supplied 11 AGND Ground Ground Analog ground 12 BG_VREF AO Ground Bandgap Voltage reference 13 AGND_CP Ground Ground Analog Ground for charge pump 14 PNEG Power Ground Integrated charge pump output. Line driver negative supply. 15 C2 - - Line driver negative flying capacitor 16 C1 - - Line driver positive flying capacitor 17 AVCC_CP Power Power Analog Supply for charge Pump 18 RT1 I HiZ Reserved. Must be connected to DGND for normal operation. 19 SS/ADDR1/HW2 I/O HiZ Interface Signal (SPI/I2C/Hardware modes) 20 MISO/ADDR0/MUTE_CTRL I/O HiZ Interface Signal (SPI/I2C/Hardware modes) 21 SCLK/SCL/HW1 I/O HiZ Interface Signal (SPI/I2C/Hardware modes) 22 MOSI/SDA/HW0 I/O HiZ Interface Signal (SPI/I2C/Hardware modes) 23 DATA2 I/O HiZ Serial DATA2 24 DATA1 I/O HiZ Serial DATA1 25 DATA_CLK I HiZ Serial data clock 26 MCLK/GPIO I/O HiZ MCLK input, General I/O 27 DGND Ground Ground Digital core ground 28 DVDD Power Power Digital core supply, internally supplied 29 Package PAD1 - - Not electrically connected, used for heat dissipation Table 1 - 28 QFN pin descriptions 1 Pin 29 is the package pad. See 28 QFN package dimensions for sizing |
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