ES9033 datasheet(86/103 Pages) ESS

86 / 103 page

0.3.1

ES9033 Datasheet Information

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

Bits

[23]

[22]

[21]

[20]

[19]

[18]

[17:14]

[13:10]

[9:1]

[0]

Default

1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 4’d0

4’d0

9’d0

1’b0

Bits

Mnemonic

Description

[23]

PLL_REG_PDB_HV

Power Down the regulators.

•

1’b0: Disable the PLL HV-regulator (default)

•

1’b1: Enable the PLL HV-regulator

[22]

PLL_REG_PDB_1V2

Power Down the regulators.

•

1’b0: Disable the PLL 1V2-regulator (default)

•

1’b1: Enable the PLL 1V2-regulator

[21:20]

RESERVED

[19]

PLL_LOW_BW

PLL low bandwidth mode.

•

1’b0: (default)

•

1’b1: Normal operation, optimum setting

[18]

PLL_CLK_OUT_DIV_PHASE_EN

•

1’b0: Disabled (default)

•

1’b1: Tune the PLL clock output divider phase

according to PLL_CLK_OUT_DIV_PHASE

[17:14]

PLL_CLK_OUT_DIV_PHASE

Sets the PLL clock output divider phase

[13:10]

PLL_CLK_OUT_DIV

Sets the Output Division (No) of the PLL.

•

9’d0: Divide by 1 (default)

•

9’d1: Divide by 2

•

9’d2: Divide by 3

•

9’dn: Divide by n+1

[9:1]

PLL_CLK_IN_DIV

Sets the PLL clock input divider.

•

9’d0: Divide by 1 (default)

•

9’d1: Divide by 2

•

9’d2: Divide by 3

•

9’dn: Divide by n+1

[0]

PLL_FB_DIV_LOAD

Writes 1 then write 0 to load CLK_FB_DIV.

ES9033 Datasheet(PDF) 86 Page - ESS Technology,Inc

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