ATMEGA64-16AI datasheet(68/393 Pages) ATMEL

68 / 393 page

ATmega64(L)

2490L–AVR–10/06

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,

PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} =

0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up

enabled state is fully acceptable, as a high-impedant environment will not notice the dif-

ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in

the SFIOR Register can be written to one to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The

user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state

({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 25 summarizes the control signals for the pin value.

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through

the PINxn Register bit. As shown in Figure 30, the PINxn Register bit and the preceding

latch constitute a synchronizer. This is needed to avoid metastability if the physical pin

changes value near the edge of the internal clock, but it also introduces a delay. Figure

31 shows a timing diagram of the synchronization when reading an externally applied

pin value. The maximum and minimum propagation delays are denoted t

pd,max and tpd,min

respectively.

Figure 31. Synchronization when Reading an Externally Applied Pin Value

Table 25. Port Pin Configurations

DDxn

PORTxn

PUD

(in SFIOR)

I/O

Pull-up

Comment

Input

Tri-state (Hi-Z)

Input

Yes

Pxn will source current if ext. pulled

low.

Input

Tri-state (Hi-Z)

Output

Output Low (Sink)

Output

Output High (Source)

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

r17

in r17, PINx

0xFF

0x00

tpd, max

XXX

tpd, min

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