ATMEGA64-16AI datasheet(92/393 Pages) ATMEL

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ATmega64(L)

2490L–AVR–10/06

EIMSK – External Interrupt

Mask Register

• Bits 7..4 – INT7 - INT0: External Interrupt Request 7 - 0 Enable

When an INT7 - INT4 bit is written to one and the I-bit in the Status Register (SREG) is

set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Con-

trol bits in the External Interrupt Control Registers – EICRA and EICRB defines whether

the External Interrupt is activated on rising or falling edge or level sensed. Activity on

any of these pins will trigger an interrupt request even if the pin is enabled as an output.

This provides a way of generating a software interrupt.

EIFR – External Interrupt Flag

• Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0

When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0

becomes set (one). If the I-bit in SREG and the corresponding Interrupt Enable bit,

INT7:0 in EIMSK, are set (one), the MCU will jump to the Interrupt Vector. The flag is

cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by

writing a logical one to it. These flags are always cleared when INT7:0 are configured as

level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled,

the input buffers on these pins will be disabled. This may cause a logic change in inter-

nal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes”

on page 70 for more information.

Bit

7654

321

0x39 (0x59)

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INT0

EIMSK

Read/Write

R/W

Initial Value

0000

000

Bit

7654

321

0x38 (0x58)

INTF7

INTF6

INTF5

INTF4

INTF3

INTF2

INTF1

INTF0

EIFR

Read/Write

R/W

Initial Value

0000

000

ATMEGA64-16AI Datasheet(PDF) 92 Page - ATMEL Corporation

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