ATMEGA64-16AI datasheet(56/393 Pages) ATMEL

56 / 393 page

ATmega64(L)

2490L–AVR–10/06

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to

the flag.

To make use of the reset flags to identify a reset condition, the user should read and

then reset the MCUCSR as early as possible in the program. If the register is cleared

before another reset occurs, the source of the reset can be found by examining the

Reset Flags.

Internal Voltage

Reference

ATmega64 features an internal bandgap reference. This reference is used for Brown-

out Detection, and it can be used as an input to the Analog Comparator or the ADC. The

2.56V reference to the ADC is generated from the internal bandgap reference.

Voltage Reference Enable

Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used.

The start-up time is given in Table 20. To save power, the reference is not always turned

on. The reference is on during the following situations:

When the BOD is enabled (by programming the BODEN Fuse).

When the bandgap reference is connected to the Analog Comparator (by setting

the ACBG bit in ACSR).

When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the

user must always allow the reference to start up before the output from the Analog Com-

parator or ADC is used. To reduce power consumption in Power-down mode, the user

can avoid the three conditions above to ensure that the reference is turned off before

entering Power-down mode.

Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 Mhz.

This is the typical value at V

CC = 5V. See characterization data for typical values at other

CC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval

can be adjusted as shown in Table 22 on page 58. The WDR – Watchdog Reset –

instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is dis-

abled and when a Chip Reset occurs. Eight different clock cycle periods can be selected

to determine the reset period. If the reset period expires without another Watchdog

Reset, the ATmega64 resets and executes from the Reset Vector. For timing details on

the Watchdog Reset, refer to page 55.

To prevent unintentional disabling of the Watchdog or unintentional change of Time-out

period, three different safety levels are selected by the fuses M103C and WDTON as

shown in Table 21. Safety level 0 corresponds to the setting in ATmega103. There is no

restriction on enabling the WDT in any of the safety levels. Refer to “Timed Sequences

for Changing the Configuration of the Watchdog Timer” on page 60 for details.

Table 20. Internal Voltage Reference Characteristics

Symbol

Parameter

Min

Typ

Max

Units

VBG

Bandgap reference voltage

1.15

1.23

1.35

tBG

Bandgap reference start-up time

µs

IBG

Bandgap reference current consumption

µA

ATMEGA64-16AI Datasheet(PDF) 56 Page - ATMEL Corporation

ATMEGA64-16AI Datasheet(HTML) 56 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL