ATMEGA64-16AI datasheet(96/393 Pages) ATMEL

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ATmega64(L)

2490L–AVR–10/06

Figure 36. Output Compare Unit, Block Diagram

The OCR0 Register is double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,

the double buffering is disabled. The double buffering synchronizes the update of the

OCR0 Compare Register to either top or bottom of the counting sequence. The synchro-

nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby

making the output glitch-free.

The OCR0 Register access may seem complex, but this is not case. When the double

buffering is enabled, the CPU has access to the OCR0 Buffer Register, and if double

buffering is disabled the CPU will access the OCR0 directly.

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOC0) bit. Forcing Compare

Match will not set the OCF0 flag or reload/clear the timer, but the OC0 pin will be

updated as if a real Compare Match had occurred (the COM01:0 bits settings define

whether the OC0 pin is set, cleared or toggled).

Compare Match Blocking by

TCNT0 Write

All CPU write operations to the TCNT0 Register will block any Compare Match that

occurs in the next timer clock cycle, even when the timer is stopped. This feature allows

OCR0 to be initialized to the same value as TCNT0 without triggering an interrupt when

the Timer/Counter clock is enabled.

Using the Output Compare

Unit

Since writing TCNT0 in any mode of operation will block all Compare Matches for one

timer clock cycle, there are risks involved when changing TCNT0 when using the Output

Compare channel, independently of whether the Timer/Counter is running or not. If the

value written to TCNT0 equals the OCR0 value, the Compare Match will be missed,

resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value

equal to BOTTOM when the counter is downcounting.

The setup of the OC0 should be performed before setting the Data Direction Register for

the port pin to output. The easiest way of setting the OC0 value is to use the Force Out-

put Compare (FOC0) strobe bit in Normal mode. The OC0 Register keeps its value even

when changing between waveform generation modes.

Be aware that the COM01:0 bits are not double buffered together with the compare

value. Changing the COM01:0 bits will take effect immediately.

OCFn (Int.Req.)

= (8-bit Comparator )

OCRn

OCxy

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMn1:0

bottom

ATMEGA64-16AI Datasheet(PDF) 96 Page - ATMEL Corporation

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