EMC6D103 datasheet(83/92 Pages) SMSC

83 / 92 page

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features

Datasheet

SMSC EMC6D103

Revision 0.3 (03-01-07)

DATASHEET

Bit[2:1] The number of edges for tach1 reading:

00=2 edges

01=3 edges

10=5 edges (default)

11=9 edges

Bit[3] Tachometer Reading Mode

0=mode 1 – standard

1=mode 2 – enhanced. (default)

Bit[4] Tach (Mode 2 only)

0=Don’t ignore first 3 edge (default)

1=Ignore first 3 tachometer edges after guard time

Note: This bit has been added to support a small sampling of fans that emit irregular tach pulses

when the PWM transitions ‘ON’. Typically, the guard time is sufficient for most fans.

Bit[7:5] PWM max stretching time

000=disable stretching

001=50msec

010=100msec

011=200msec

100=400msec

101=600msec

110=800msec (default)

111=950msec

PWM Max stretch time determines the maximum time for monitoring the tach input. If stretching is

disabled, the tach will only be monitored when the PWM duty cycle is ‘ON’.

8.2.41

Registers 94h-96h: PWMx Option Registers

These registers become read only when the Lock bit is set. Any further attempts to write to these

registers shall have no effect.

Bits[1:0] Tachs reading registers associated with PWMx are updated: (Mode 2 only)

00=once a second (default)

Table 8.62 Registers 94h-96h: PWMx Option Registers

Address

Read/

Write

Name

Bit 7

(MSb)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSb)

Default

Value

94h

R/W

PWM1 Option

RES

OPP

GRD1

GRD0

SZEN

UPDT1

UPDT0

0Ch

95h

R/W

PWM2 Option

RES

OPP

GRD1

GRD0

SZEN

UPDT1

UPDT0

0Ch

96h

R/W

PWM3 Option

RES

OPP

GRD1

GRD0

SZEN

UPDT1

UPDT0

0Ch

EMC6D103 Datasheet(PDF) 83 Page - SMSC Corporation

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