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RT600 Datasheet(PDF) 19 Page - NXP Semiconductors |
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RT600 Datasheet(HTML) 19 Page - NXP Semiconductors |
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19 / 171 page ![]() RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2024. All rights reserved. Product data sheet Rev. 2.2 — 25 January 2024 19 of 173 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs PIO0_10/ TDI E2 J3 L16 Z I/O 0 PIO0_10 — General-purpose digital input/output pin. In boundary scan mode: TDI (Test Data In). I/O 1 FC1_CTS_SDA_SSEL0 — Flexcomm 1: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I 2 SCT0_GPI7 — Pin input 7 to SCTimer/PWM. O 3 SCT0_OUT7 — SCTimer/PWM output 7. O 4 CTIMER1_MAT3 — 32-bit CTimer1 match output 3. I/O 5 FC0_SSEL2 — Flexcomm 0: SPI slave select 2. 6 R — Reserved. 7 R — Reserved. I/O 8 SEC_PIO0_10 — Secure GPIO pin. PIO0_11/ TDO E1 L1 K13 Z I/O 0 PIO0_11 — General-purpose digital input/output pin. In boundary scan mode: TDO (Test Data Out). I/O 1 FC1_RTS_SCL_SSEL1 — Flexcomm 1: USART request-to-send, I2C clock, SPI slave select 1. I 2 SCT0_GPI0 — Pin input 0 to SCTimer/PWM. O 3 SCT0_OUT8 — SCTimer/PWM output 8. I 4 CTIMER_INP2 — Capture input 2 to CTIMER input muxes. I/O 5 FC0_SSEL3 — Flexcomm 0: SPI slave select 3. 6 R — Reserved. 7 R — Reserved. I/O 8 SEC_PIO0_11 — Secure GPIO pin. PIO0_12/ CH1A K1 E3 F15 Z I/O; AI 0 PIO0_12/CH1A — General-purpose digital input/output pin. Analog input 1A. Can optionally be paired with CH1B for differential input on ADC channel 1. I/O 1 FC1_SSEL2 — Flexcomm 1: SPI slave select 2. I 2 SCT0_GPI2 — Pin input 2 to SCTimer/PWM. O 3 SCT0_OUT2 — SCTimer/PWM output 2. I 4 CTIMER_INP3 — Capture input 3 to CTIMER input muxes. 5 R — Reserved. 6 R — Reserved. 7 R — Reserved. I/O 8 SEC_PIO0_12 — Secure GPIO pin. Table 4. Pin description …continued Symbol Description |
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