RT600 datasheet(83/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.2 — 25 January 2024

83 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in

multiples of Tcy(WDCLK)  4.

• The Watchdog Clock (WDCLK) uses the WDOSC as the clock source.

10.18.4 Real Time Clock (RTC) timer

The RTC timer is a 32-bit timer which counts down from a preset value to zero. At zero,

the preset value is reloaded and the counter continues. The RTC timer uses the 32.768

kHz clock input to create a 1 Hz or 1 kHz clock. Selectable on-chip crystal load capacitors

are available for the RTC Oscillator.

10.18.5 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each

channel can be programmed with an independent time interval, and each channel

operates independently from the other channels.

10.18.5.1 Features

• 24-bit interrupt timer.

• Four channels independently counting down from individually set values.

• Repeat and one-shot interrupt modes.

10.18.6 OS/Event Timer

An OS/EVENT Timer module will provide a common time-base between the two CPUs for

event synchronization and time-stamping.

The OS/EVENT Timer is comprised of a shared, free-running counter readable by each

CPU and individual match and capture registers for each CPU.

The shared and local counters in this module will be implemented using Gray code. This

will enable them to be read asynchronously by the processing domains.

The main counter in the OS/EVENT Timer module begins counting immediately following

power-up and continues counting through any subsequent system resets (except those

caused by a new POR).

10.18.6.1 Features

• 64-bit Gray code counter. Using Gray code means that the timer can run at a a

frequency unrelated to either CPU clock and can still be read by either CPU without a

synchronization delay. Gray code is a reflected binary code that changes in a single

bit position for each increment.

• Separate functions for each CPU:

• A capture register can copy the main counter value when triggered by a CPU

request.

• A match register can be compared to the main counter and can optionally generate an

interrupt or wake-up event

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