RT600 datasheet(66/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.2 — 25 January 2024

66 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

[1] This is a suggested configuration of cacheable and non-cacheable regions, See Section 10.12.10.1 below.

[2] The HiFi 4 does not use AHB to access this space.

[3] AHB peripherals on other AHB matrix ports are not accessible to the HiFi 4. See Section 10.12.9 “AHB

peripherals”.

10.12.10.1 Using cacheable and non-cacheable memory regions

The cacheable and non-cacheable regions indicated in the table above and elsewhere in

this chapter are recommended (not forced by hardware) in order to insure that the TCMs

are not in cacheable space. If this is not done, TCM accesses will use additional power

while providing no performance improvement. Cacheable and non-cacheable regions

may be user configured via software tools (e.g. the linker used to create HiFi 4 code), and

at run time via API calls.

The recommended configuration allows the user to control cache usage for the large

shared memory via the two logical address ranges that access the same physical

memories. By selecting the address for specific memory usage (as shown in Table 15),

the cache will, or will not, be used for that access.

For example, HiFi4 code may always be placed at cacheable addresses. Data that is

accessed as a long sequential stream (and therefore not useful to cache) may be placed

in non-cacheable addresses. Avoiding the cache when it is not needed will save power

and leave more cache space for operations that can take advantage of it.

In addition, cacheing certain areas, such as data that is altered through a different path

such as DMA, or peripheral registers, can cause improper operation.

10.13 System control

10.13.1 Clock sources

The RT600 supports three external and three internal clock sources:

• 12 MHz Free Running Oscillator

• 48/60 MHz Free Running Oscillator (FRO).

• 1 MHz Low-Power Internal Oscillator.

• Crystal oscillator.

• 32 kHz Crystal Oscillator

• External Clock Input pin (50 MHz maximum)

10.13.1.1 12 MHz Free Running Oscillator (FRO)

The FRO 12 MHz oscillator provides the default clock at reset and provides a clean

system clock shortly after the supply pins reach operating voltage. This FRO oscillator,

factory trimmed for accuracy, that can optionally be used as a system clock as well as

other purposes

10.13.1.2 48/60 MHz Free Running Oscillator (FRO)

Selectable 48 MHz or 60 MHz FRO oscillator, factory trimmed for accuracy, that can

optionally be used as a system clock as well as other purposes.

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