RT600 datasheet(15/171 Pages) NXP

15 / 171 page

RT600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.2 — 25 January 2024

15 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

7. Pinning information

Table 4 shows the pin functions available on each pin, and for each package. These

functions are selectable using IOCON control registers.

Some functions, such as ADC or comparator inputs, are available only on specific pins

when digital functions are disabled on those pins. By default, the GPIO function is

selected except on pins PIO2_25 and PIO2_26, which are the serial wire debug pins. This

allows debug to operate through reset.

All GPIO pins have all pull-ups and pull-downs turned off at reset. This prevents power

loss through pins prior to software configuration. All GPIO pins are fail safe up to 3.6 V

when VDDIO supply = 0 V except following pins (PIO1_18 to PIO1_31, PIO2_0 to

PIO2_8, PIO0_21, PIO0_22, and PIO0_23 pins). See GPIO pin diagrams for

configuration options Figure 32 “Simplified fail-safe GPIO pins” and Figure 33 “Simplified

high-speed GPIO pins”.

The state of pins PIO1_15, PIO1_16, and PIO1_17 at Reset determine the boot source for

the part or if the ISP handler is invoked.

The JTAG functions TRST, TCK, TMS, TDI, and TDO, are selected on pins PIO0_7 to

PIO0_11 by hardware when the part is in boundary scan mode. The SPI Flash Recovery

Boot pin functions are multiplexed with the JTAG boundary scan functions. To ensure

boundary scan mode is not inadvertently entered, the TRST pin should be externally tied

low using a weak pull-down resistor (100 kohm) to ensure proper SPI Flash Recovery

Boot operation.

Table 4.

Pin description

Symbol

Description

PIO0_0

H17

Z I/O 0

PIO0_0 — General-purpose digital input/output pin.

I/O 1

FC0_SCK — Flexcomm 0: USART, SPI, or I2S clock.

R — Reserved.

CTIMER0_MAT0 — 32-bit CTimer0 match output 0.

I2S_BRIDGE_CLK_IN — Allows I2S bypass by re-routing

this function to a pin that includes the

I2S_BRIDGE_CLK_OUT function.

GPIO_INT_BMAT — Output of the pin interrupt pattern

match engine.

R — Reserved.

I/O 8

SEC_PIO0_0 — Secure GPIO pin.

RT600 Datasheet(PDF) 15 Page - NXP Semiconductors

RT600 Datasheet(HTML) 15 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL