RT600 datasheet(75/171 Pages) NXP

75 / 171 page

RT600

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Product data sheet

Rev. 2.2 — 25 January 2024

75 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

10.16.1 Features

• Pin interrupts:

– Up to eight pins can be selected from all GPIO pins on ports 0 and 1 as

edge-sensitive or level-sensitive interrupt requests. Each request creates a

separate interrupt in the NVIC.

– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

– Level-sensitive interrupt pins can be HIGH-active or LOW-active.

– Pin interrupts can wake up the device from sleep mode and deep-sleep mode.

• Pattern match engine:

– Up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute

to a boolean expression. The boolean expression consists of specified levels

and/or transitions on various combinations of these pins.

– Each bit slice minterm (product term) comprising of the specified boolean

expression can generate its own, dedicated interrupt request.

– Any occurrence of a pattern match can also be programmed to generate an RXEV

notification to the CPU. The RXEV signal can be connected to a pin.

– Pattern match can be used in conjunction with software to create complex state

machines based on pin inputs.

– Pattern match engine facilities wake-up only from active and sleep modes.

10.17 Communications peripherals

10.17.1 High-speed USB Host/Device interface (USB1)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

10.17.1.1 USB1 device controller

The device controller enables 480 Mbit/s data exchange with a USB host controller. It

consists of a register interface, serial interface engine, endpoint buffer memory. The serial

interface engine decodes the USB data stream and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

Features

• Fully compliant with USB 2.0 Specification (high speed).

• Supports 12 physical (6 logical) endpoints with up to 8 kB endpoint buffer RAM.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint Maximum packet size selection (up to USB maximum specification) by

software at run time.

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