RT600 datasheet(76/171 Pages) NXP

76 / 171 page

RT600

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Product data sheet

Rev. 2.2 — 25 January 2024

76 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

• While USB is in the Suspend mode, the RT600 can enter one of the reduced power

modes and wake up on USB activity.

• Double buffer implementation for Bulk and Isochronous endpoints.

10.17.1.2 USB1 host controller

The host controller enables high speed data exchange with USB devices attached to the

bus. It consists of register interface and serial interface engine. The register interface

complies with the Enhanced Host Controller Interface (EHCI) specification.

Features

• EHCI compliant.

• Two downstream ports.

• Supports per-port power switching.

10.17.2 FlexSPI Flash Inerface

The Flexible Serial Peripheral Interface (FlexSPI) host controller supports up to two SPI

channels and up to 4 external devices. Each channel supports Single/Dual/Quad/Octal

mode data transfer (1/2/4/8 bidirectional data lines).

FlexSPI flash interface with 32 KB cache and dynamic decryption for execute-in-place and

supports DMA.

10.17.2.1 Features

• FlexSPI is compliant to JEDEC’s JESD151 v1.0 for xSPI standard specification

• Flexible sequence engine (LUT table) to support various vendor devices.

– Serial NOR Flash: XccelaFLash, HyperFlash, EcoXiP Flash, Octa Flash, and all

QSPI flash devices

– Serial NAND Flash

– Serial pSRAM: HyperRAM, Xccela RAM (IoTRAM)

– FPGA device

• Flash access mode

– Single/Dual/Quad/Octal mode

– SDR/DDR mode

– Individual/Parallel mode

• Support sampling clock mode:

– Internal dummy read strobe looped back internally

– Internal dummy read strobe looped back from pad

– Flash provided read strobe

• Automatic Data Learning to select correct sample clock phase

• Memory mapped read/write access by AHB Bus

– AHB RX Buffer implemented to reduce read latency. Total AHB RX Buffer size: 256

* 64 Bits

– 16 AHB masters supported with priority for read access

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