RT600 datasheet(81/171 Pages) NXP

81 / 171 page

RT600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.2 — 25 January 2024

81 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

The timer/counter is designed to count cycles of the system derived clock or an

externally-supplied clock. It can optionally generate interrupts, generate timed DMA

requests, or perform other actions at specified timer values, based on four match

registers. Each timer/counter also includes two capture inputs to trap the timer value when

an input signal transitions, optionally generating an interrupt.

10.18.1.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• Counter or timer operation.

• Up to four 32-bit captures can take a snapshot of the timer value when an input signal

transitions. A capture event may also optionally generate an interrupt. The number of

capture inputs for each timer that are actually available on device pins may vary by

device.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

– Shadow registers are added for glitch-free PWM output.

• For each timer, up to four external outputs corresponding to match registers with the

following capabilities (the number of match outputs for each timer that are actually

available on device pins may vary by device):

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

• Up to two match registers can be used to generate timed DMA requests.

• The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

• Up to four match registers can be configured for PWM operation, allowing up to three

single edged controlled PWM outputs. (The number of match outputs for each timer

that are actually available on device pins may vary by device.)

10.18.2 SCTimer/PWM

The SCTimer/PWM allows a wide variety of timing, counting, output modulation, and input

capture operations. The inputs and outputs of the SCTimer/PWM are shared with the

capture and match inputs/outputs of the 32-bit general-purpose counter/timers.

The SCTimer/PWM can be configured as two 16-bit counters or a unified 32-bit counter. In

the two-counter case, in addition to the counter value the following operational elements

are independent for each half:

• State variable.

• Limit, halt, stop, and start conditions.

• Values of Match/Capture registers, plus reload or capture control values.

RT600 Datasheet(PDF) 81 Page - NXP Semiconductors

RT600 Datasheet(HTML) 81 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL