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RT600 Datasheet(PDF) 80 Page - NXP Semiconductors |
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RT600 Datasheet(HTML) 80 Page - NXP Semiconductors |
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80 / 171 page ![]() RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2024. All rights reserved. Product data sheet Rev. 2.2 — 25 January 2024 80 of 173 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs • Data for all I2S traffic within one Flexcomm Interface uses the Flexcomm Interface FIFO. The FIFO depth is 8 entries. • Left justified and right justified data modes. • DMA support using FIFO level triggering. • TDM (Time Division Multiplexing) with a several stereo slots and/or mono slots is supported. Each channel pair can act as any data slot. Multiple channel pairs can participate as different slots on one TDM data line. • The bit clock and WS can be selectively inverted. • Sampling frequencies supported depends on the specific device configuration and applications constraints (for example, system clock frequency and PLL availability.) but generally supports standard audio data rates. See the data rates section in I2S chapter in the RT6xx user manual to calculate clock and sample rates. 10.17.5 High-Speed SPI interface (Flexcomm Interface 14) An additional, stand-alone SPI module is provided. This will be a high-speed SPI able to provide 50 MHz transfer rates. Functionally, it is identical to the SPI Flexcomm interfaces 0 to 7. Excluding delays introduced by external device and PCB, the maximum supported bit rate for SPI master mode (transmit/receive) is 50 Mbit/s. The maximum supported bit rate for SPI slave mode (receive) is 50Mbit/s and for SPI slave mode (transmit) is 35 Mbit/s. 10.17.6 I3C interface The MIPI Alliance Improved Inter-Integrated Circuit (MIPI I3C) brings major improvements in use and power over I2C, and provides an alternative to SPI for mid-speed applications.The I3C bus is designed to support future sensor interface architectures, widely expected in Internet-of-Things applications. The I3C bus is intended to be used by microcontrollers (MCU) and application processors (AP) to connect to sensors, actuators, and other MCUs (as slaves). Connecting an MCU to other MCUs and connecting an AP to an MCU are considered to be the major use cases. 10.17.6.1 Features • In-band interrupts: interrupts can go from Slave to Master without extra wires, such that the Master knows which Slave sent the interrupt. • In-band command codes (Common Command Codes (CCC)) • Dynamic addressing • Multi-master / multi-drop • Hot-Join • I2C compatibility. Note that I2C compatibility has limitations. Please refer to user manual for further details. 10.18 Counter/timer peripherals 10.18.1 General-purpose 32-bit timers/external event counter The RT600 includes five general-purpose 32-bit timer/counters. |
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