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RT600 Datasheet(PDF) 102 Page - NXP Semiconductors |
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RT600 Datasheet(HTML) 102 Page - NXP Semiconductors |
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102 / 171 page  RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2024. All rights reserved. Product data sheet Rev. 2.2 — 25 January 2024 102 of 173 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs [1] Based on the power API library from the SDK software package available on nxp.com. [2] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C). VDD_AO1V8 = VDD1V8 = VDDIO_0/1/2 = VDDA_ADC1V8 = 1.8 V. VDDA_ADC3V3 = VREFP = USB1_VDD3V3 = 3.3 V [3] Clock source IRC. PLL disabled. [4] Characterized through bench measurements using typical samples. [5] Compiler settings: IAR C/C++ Compiler for Arm ver 8.32.3, optimization level 0, optimized for time off. [6] All peripheral clocks disabled. [7] Clock source IRC. PLL enabled. [1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), All power supplies to = 1.8 V except USB1_VDD3V3 = 3.3 v [2] Characterized through bench measurements using typical samples. [3] Guaranteed by characterization, not tested in production. [4] In deep-sleep mode, the VDDCORE voltage is set to 0.7V. Table 28. Static characteristics: Power consumption in deep-sleep mode[4] Tamb = -20 C to +85C, unless otherwise specified, Symbol Parameter Conditions Min Typ[1][2] Max[3] Unit IVDD1V8 supply current Deep-sleep mode; SRAM (128 KB) powered, Internal LDO enabled. Array On, Periphery Off - 109 - A IVDD1V8_1 supply current Deep-sleep mode; SRAM (128 KB) powered, Internal LDO enabled. Array On, Periphery Off - 65 - A IVDDCORE supply current Deep-sleep mode; SRAM (32 KB) powered, Internal LDO disabled. Array On, Periphery Off Tamb = 25 C - 75 - A IVDDCORE supply current Deep-sleep mode; SRAM (128 KB) powered, Internal LDO disabled. Array On, Periphery Off Tamb = 25 C - 77 - A IVDDCORE supply current Deep-sleep mode; SRAM (4.5 MB) powered, Internal LDO disabled. Array On, Periphery Off Tamb = 25 C - 190 - A IVDD_AO1V8 supply current Deep-sleep mode; SRAM (128 KB) powered, Internal LDO enabled. Array On, Periphery Off - 0.6 - A IVDDIO_0 supply current Deep-sleep mode; SRAM (128 KB) powered, Internal LDO enabled. Array On, Periphery Off - 7.0 - A IVDDIO_1 supply current Deep-sleep mode; SRAM (128 KB) powered, Internal LDO enabled. Array On, Periphery Off - 0.9 - A IVDDIO_2 supply current Deep-sleep mode; SRAM (128 KB) powered, Internal LDO enabled. Array On, Periphery Off - 6.4 - A IVDDA_ADC1V8 supply current Deep-sleep mode; SRAM (128 KB) powered, Internal LDO enabled. Array On, Periphery Off - 0.1 - A IVDDA_BIAS supply current Deep-sleep mode; SRAM (128 KB) powered, Internal LDO enabled. Array On, Periphery Off - 0.1 - A IVREFP supply current Deep-sleep mode; SRAM (128 KB) powered, Internal LDO enabled. Array On, Periphery Off - 0.1 - A IUSB1_VDD3V3 supply current Deep-sleep mode; SRAM (128 KB) powered, Internal LDO enabled. Array On, Periphery Off - 0.1 - A |
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