RF226AP datasheet(39/46 Pages) NXP

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Table 14. Start-up specification

Parameter

Conditions

Min

Typ

Max

Unit

Minimum reset time Crystal oscillator

Maximum DLL

calibration time

700

μs

Upon power-up and release from reset, the chip has its 160 MHz differential clock IO

buffer tri-stated. It has the internal crystal oscillator enabled to generate a 40 MHz clock,

and that clock is driven to internal components to allow configuration via the I2C and/or

the LLCP interfaces.

The firmware download and further configuration are possible over either the I2C or

LLCP (running at 100 Mbps) interfaces.

After firmware download and a command to calibrate the DLL, the completion of

calibration is reported in a register that can be polled over the LLCP or I2C interfaces.

The 160 MHz differential clock IO output can be enabled with a firmware command over

the LLCP or I2C interfaces subsequent to DLL calibration.

3.9 Specification of auxiliary functions

3.9.1 Auxiliary ADC

The auxiliary ADC will be used for internal calibration and during test.

Internal signals are routed to the AUX ADC via the analog test bus.

External signals are can be applied to the AUX ADC via the ATEST1 to ATEST4 pins,

without using the analog testbus. The AUX ADC MUX has inputs directly connected to

the ATEST pads. Both single-ended and differential external signals can be connected to

the AUX ADC.

This table shows an auxiliary ADC specification.

Table 15. Auxiliary ADC specification

Parameter

Conditions

Min

Typ

Max

Unit

Conversion time

per sample

11 bits, 20 MHz

internal ADC clock

0.6

1.0

µs

Table continues on the next page...

Electrical characteristics

RF112L0H Transceiver Data Sheet, Rev. A, 12/2020

NXP Semiconductors

Preliminary

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