RF226AP datasheet(5/46 Pages) NXP

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receiver chain. This allows the receiver AGC algorithm, located on the baseband chip, to

observe the wideband signal level and optimize the receiver gain for best performance.

The interface allows quick updates of the transmitter and receiver gains.

This figure shows top level block diagram of the RF112L0H Transceiver.

aaa-037054

AUX ADC

SYNTHESIZERS

LNA

5/8

AND x4

3/2

LNA

1/4

1/2

ATEST4

ATEST3

ATEST2

ATEST1

RX1_HB_IN

RX1_LB_IN

RO1_LB_IN

RO1_HB_IN

ROBB2_OUT_Q_P

RO2_HB_IN

RX2_LB_IN

TX_LB_OUT

TX_HB_OUT

RX2_HB_IN

ROBB2_OUT_Q_N

ROBB2_OUT_I_N

ROBB2_OUT_I_P

OTP

DIGITAL CORE

1/2

LNA

I2C

LVDS

OUT

1/4

LNA

5/2

LNA

1/2

Frac-N

Synt

TRX Synt

Obs 2 Synt

Obs 1 Synt

Frac-N

Synt

Frac-N

Synt

LVDS

Figure 2. RF112L0H Transceiver block diagram

The TRX sub-system is capable of operating in TDD mode in either high band or low

band. The TRX consists of one high band transceiver and one low band transceiver which

share baseband filters and analog interfaces. The transceivers each have one transmitter

and two identical receivers, the transmitter and one of the receivers share the same LO,

the second receiver LO-phases are generated independently from the same synthesizer as

the transmit-receive-pair. The LO generation for the TRX sub-system is kept running all

the time, to keep the LO-phase relations fixed after chip power-on.

Introduction

RF112L0H Transceiver Data Sheet, Rev. A, 12/2020

NXP Semiconductors

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