RF226AP datasheet(7/46 Pages) NXP

7 / 46 page

The digital part of RF112L0H consists of an ASP and a number of digital hardware

blocks, and interfaces both with the analogue part - via an RS bus, signals, and clocks -

and with the outside world - via LLCP and I2C interfaces. The internal clock frequency is

160 MHz in normal operation, during boot a 40 MHz clock is used. The digital part is

used to control and calibrate the analog part of the chip, both RF and baseband signal

interfaces are analog.

2 Pin assignments

2.1 RF226R Transceiver QFN layout diagrams

This figure shows the complete view of the RF226R QFN diagram.

RX1_LB_IN

TEST_MODE

VDD_RX1

DTEST1

RX1_HB_IN

DTEST2

ATEST1

RX2_HB_IN

ATEST2

VDD_TRX2

TX_HB_OUT

VDD_TRX2

VDD_XO

TX_LB_OUT

ATEST3

VDD_TRX2

ATEST4

RX2_LB_IN

RO1_LB_IN

VDD_RO2

VDD_RO1

RO2_HB_IN

RO1_HB_IN

ROBB2_OUT_Q_P

VDD_BB1

ROBB2_OUT_Q_N

ROBB1_OUT_I_P

ROBB2_OUT_I_N

ROBB1_OUT_I_N

ROBB2_OUT_I_P

aaa-037105

65 GND

Figure 4. RF226R Transceiver QFN layout

Pin assignments

RF112L0H Transceiver Data Sheet, Rev. A, 12/2020

NXP Semiconductors

Preliminary

Confidential Proprietary

RF226AP Datasheet(PDF) 7 Page - NXP Semiconductors

RF226AP Datasheet(HTML) 7 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL