RF226AP datasheet(4/46 Pages) NXP

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TX_HB_LO_I

I/Q

TX_LB_LO_Q

TX_LB_LO_I

TX_HB_LO_Q

RX2_HB_LO_I

I/Q

RX2_LB_LO_Q

RX2_LB_LO_I

RX2_HB_LO_Q

RO1_HB_LO_I

I/Q

RO1_LB_LO_Q

RO1_LB_LO_I

RO1_HB_LO_Q

RO2_HB_LO_I

RO2_HB_LO_Q

RX1_HB_LO_I

RX1_LB_LO_Q

RX1_LB_LO_I

RX1_HB_LO_Q

RO1 Path

RO2 Path

TX Path

RX2 Path

RX1 Path

Figure 1. RF112L0H Transceiver Simplified model

The RF112L0H Transceiver uses a direct conversion architecture for both RX and TX.

The chip has independent synthesizers for each sub-system driven from a common

reference. The frequency reference can be a 40 MHz crystal or external oscillator. The

input reference is multiplied internally by 4 and can be routed to an output differential

pair for use as a low jitter 160 MHz frequency reference by other devices in the system.

The gain in receive mode should be controlled by the baseband IC. The receive chain has

low noise and high dynamic range. The analog baseband filters have on-chip calibration

and supports 20, 40, or 80 MHz modulation bandwidth. An internal crystal oscillator is

implemented to enable usage of a low cost crystal. The reference frequency can be fine-

tuned to minimize the frequency error. A LVDS clock output is included to provide a

reference clock to the baseband chip. An auxiliary ADC is implemented for calibration

purposes and to serve various external functions like power and temperature

measurements.

The two interfaces, a traditional low-speed I2C, and a low complexity high-speed custom

LVDS buses are available for configuration and bi-directional data exchanges with the

baseband. HS LLCP as main, LS I2C as secondary. The high speed interface can be used

to provide a continuous stream of RF envelope detector samples after the LNA in each

Introduction

RF112L0H Transceiver Data Sheet, Rev. A, 12/2020

Preliminary

NXP Semiconductors

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