33989 datasheet(29/66 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33989

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Figure 16. Simplified State Machine in Debug Modes

LOGIC COMMANDS AND REGISTERS

SPI INTERFACE AND REGISTER DESCRIPTION

Table 7 illustrates a register, an 8-bit SPI. The first three

bits are used to identify the internal SBC register address. Bit

four is a read/write bit. The last four bits are Data Send from

MCU to SBC, or read back from SBC to MCU.

There is no significance during write operation state of

MISO.

During read operation only the final four bits of MISO have

a meaning (content of the accessed register).

The following tables describe the SPI register list, and

Registers reset value is also described along with the reset

condition. Reset condition is the condition causing the bit to

be set at the reset value.

Read operation: R/W Bit = 0

Write operation: R/W Bit = 1

Possible reset conditions include:

Wake-up

Normal Request

Stand-by Debug

Normal

: Trig

ger

Stand-by

SPI: Stand-by Debug

I: N

orm

al D

Reset

Reset Counter

(3.4 ms) Expired

WD: Time-out 350 ms

SPI: Normal Debug

Normal Debug

Stop Debug

Wake-up

(1) If Stop mode entered, it is entered without watchdog, no matter the WDSTOP bit.

(E) Debug mode entry point (Step 5 of the Debug mode entering sequence).

(R) Represents transitions to Reset mode due to VDD1 low.

Sleep

Stop (1)

Table 7. Data Format Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W

SBC Reset:

Power-On Reset POR

SBC Mode Transition: NR2R - Normal Request to Reset Mode

NR2N - Normal Request to Normal Mode

NR2STB - Normal Request to Standby

Mode

N2R - Normal to Reset Mode

STB2R - Standby to Reset Mode

STO2R - Stop to Reset Mode

STO2NR - Stop to Normal Request

SBC Mode:

RESET - SBC in Reset Mode

33989 Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc

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