33989 datasheet(42/66 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33989

TYPICAL APPLICATIONS

SUPPLEMENTAL APPLICATION NOTES

Power Up and VDD1 Going Low with Sleep Mode as

Default Low Power Mode Selected

The first part of the graph is the same as the previous

figure. If VDD1 is pulled below the VDD1 under voltage reset

(typ 4.6 V) for instance by an over current or short circuit (ex

short to 4 V), and if the low power mode previously selected

was sleep mode and if the BATFAIL flag has been cleared,

the SBC enters reset mode for a time period of 100 ms. The

pin WD stays high, but the high level (VOH) follows the VDD1

level.The reset and interrupt pins are low. After the 100 ms,

the SBC goes into sleep mode. VDD1 and V2 are off (The

following figure is an example where VDD1 is shorted to 4 V,

and after 100 ms the SBC enters sleep mode.

Figure 25. Power up and VDD1 Going Low with Sleep Mode as Default Low Power Mode Selected

WAKE-UP TIMINGS — SLEEP MODE

The paragraphs below describe the wake-up events from

sleep mode, and the sequence of the signals at the SBC

level. The wake-up time described is the time from the wake-

up event to the SBC reset pin release. The wake-up time is

the sum of several timings: wake-up signal detection, VDD1

regulator start-up and decoupling capacitor charge, and reset

time. At the end of the reset time, the reset pin goes from low

to high and the MCU is ready to start software operations.

LX Wakes up SBC from Sleep Mode

Below is the case where the SBC is in sleep mode and is

awaked by LX positive edge.

Figure 26.

• T1 (LX high level to VDD1 turn on): typ 100 µs.

•T2: VDD1 rising time is dependent on the capacitor and

the load connected to VDD1. It can be approximated by

the capacitor charging time with the regulator output

current limitation: T2 = (C x U)/I. With C = 100 mF,

IDD1 = 200 mA min., U = 5 V so T2 = 2.5 ms).

• T3 (VDD1>RST-TH (4.6 V by default) to reset high):

parameter Rest dur: 4 ms max.

• The total time is 6.6 ms in this example.

CAN Wake-Up

The following case describes the signal for CAN wake up.

Refer to page 49 for more details on CAN wake up signals

and the TCAN analysis.

SBC in R e s e t

m o de

(B A T F A IL fla g

mu s t b e c le a re d )

SB C in Sle e p m o d e

100 ms

S B C in N o rm a l re qu es t

mo d e

SBC in N o rm a l

mo d e

SBC in

R ESE T

mo d e

350 ms

VDD1

SPI (CS)

INT

RST

Reset every 350 ms

Write Watchdog

each X ms

No problem on

Watchdog period

VDD1

RST

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