33989 datasheet(35/66 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33989

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Timing Register (TIM1/2)

This register is composed of two registers:

1. TIM1–controls the watchdog timing selection as well as

the window or timeout option. TIM1 is selected when

bit D3 is 0. Please see Table 24.

2. TIM2–is used to define the timing for the cyclic sense

and forced wake-up function. TIM2 is selected when bit

D3 is read operation it is not allowed in either TIM1 or

TIM2 registers. Please see Table 26.

Figure 17. Window Watchdog

Figure 18. Timeout Watchdog

Table 24. TIM1 Register

TMI1

$101B

WDW

WDT1

WDT0

—

Reset Value

—

Reset Condition

—

POR, RST

Table 25. TIM1 Control Bits

WDW

WDT1

WDT0

Timing (ms)

Parameter

Watchdog Period 1

No Window Watchdog

Watchdog Period 2

100

Watchdog Period 3

350

Watchdog Period 4

Watchdog Period 1

Window Watchdog Enabled (Window

Length is Half the Watchdog Timing)

Watchdog Period 2

100

Watchdog Period 3

350

Watchdog Period 4

WD Timing x 50%

Watchdog Period

(WD Timing Selected by TIM1 Bit WDW=1)

Window Open

for Watchdog Clear

Watchdog Period

(WD Timing Selected by TIM1 Bit WDW=1)

Table 26. TIM2 Register

TMI2

$101B

CSP2

CSP1

CSP0

—

Reset Value

—

Reset Condition

—

POR, RST

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