XRT79L71IB datasheet(30/109 Pages) EXAR

30 / 109 page

XRT79L71

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0

TxUEN/

TxPEN

Transmit UTOPIA Interface Block - Write Enable/Transmit POS-PHY Inter-

face - Write Enable:

The function of this input pin depends upon whether the XRT79L71 has been

configured to operate in the ATM UNI or PPP Mode.

ATM UNI Mode Operation - TxUEN - Transmit UTOPIA Interface - Write

Enable Input pin:

This active-"Low" signal, from the ATM Layer processor enables the data on the

Transmit UTOPIA Data Bus to be latched and written into the TxFIFO on the ris-

ing edge of TxUClk. When this signal is asserted (e.g., pulled to a logic "Low"

level), then the contents of the byte or word that is present, on the Transmit UTO-

PIA Data Bus (TxUData[15:0]), will be latched into the Transmit UTOPIA Inter-

face block, on the rising edge of TxUClk.

When this signal is negated, then the Transmit UTOPIA Data bus inputs will be

tri-stated.

PPP Mode Operation - TxPEN - Transmit POS-PHY Interface - Write Enable

Input pin:

This active-"Low" signal, from the Link Layer processor enables the data on the

Transmit POS-PHY Data Bus to latched and be written into the TxFIFO on the

rising edge of TxPClk. When this signal is asserted (e.g., pulled to a logic "Low"

level), then the contents of the byte or word that is present, on the Transmit POS-

PHY Data Bus (TxPData[15:0]), will be latched into the Transmit POS-PHY Inter-

face block, on the rising edge of TxPClk.

When this signal is negated, then the Transmit POS-PHY Data bus inputs will be

tri-stated.

NOTE: This input pin is only active if the XRT79L71 has been configured to

operate in the ATM UNI or PPP Mode. The user should tie this input pin

to GND to operate the XRT79L71 in either the Clear-Channel Framer or

High-Speed HDLC Controller Mode.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB Datasheet(PDF) 30 Page - Exar Corporation