XRT79L71IB datasheet(95/109 Pages) EXAR

95 / 109 page

XRT79L71

REV. 1.0.0

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

TRANSMIT PAYLOAD DATA INPUT INTERFACE

TRANSMIT PAYLOAD DATA INPUT INTERFACE - TIMING REQUIREMENTS

t11

TxUClav signal valid (not Hi-Z) from first TxUClk rising edge of

valid and correct TxUAddr[4:0]

3.6

9.7

t12

TxUClav signal Hi-Z from first TxUClk rising edge of different

TxUAddr[4:0]

3.6

9.7

TABLE 16: TIMING INFORMATION FO RTHE TRNASMIT PAYLOAD DATA INPUT INTERFACE BLOCK

Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNITS

CONDITIONS

Transmit Payload Data Input Interface - Loop-Timed/Serial Mode (See

Figure 17)

Payload data (TxSer) set-up time to rising edge of

RxOutClk

Payload data (TxSer) hold time, from rising edge of

RxOutClk

RxOutClk to TxFrame output delay

RxOutClk to TxOHInd output delay

Transmit Payload Data Input Interface - Local Timed/Serial Mode (See

Figure 18)

Payload data (TxSer) set-up time to rising edge of

TxInClk

Payload data (TxSer) hold time, from rising edge of

TxInClk

TxFrameRef set-up time to rising edge of TxInClk

Framer IC is

Frame Slave

TxFrameRef hold-time, from rising edge of TxInClk

Frame IC is

Frame Slave

TxInClk to TxOHInd output delay

t10

TxInClk to TxFrame output delay

Transmit Payload Data Input Interface - Looped-Timed/Nibble Mode (See

Figure 19)

t11

TxNib set-up time to third rising edge of RxOutClk

t12

Payload Nibble hold time, from latching edge of

RxOutClk

t13

TxNibClk to TxNibFrame output delay

DS3 Applications

E3 Applications

t13A

Max Delay of Rising Edge of TxNibClk to Data Valid

on TxNib[3:0]

DS3 Applications

E3 Applications

Transmit Payload Data Input Interface - Local-Timed/Nibble Mode (See

Figure 20

TABLE 15: TIMING INFORMATION FOR THE TRANSMIT UTOPIA INTERFACE BLOCK

SYMBOL

PARAMETER

MIN.TYP

MAX.UNITS

XRT79L71IB Datasheet(PDF) 95 Page - Exar Corporation

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