XRT79L71IB datasheet(33/109 Pages) EXAR

33 / 109 page

XRT79L71

REV. 1.0.0

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

TxTSX/

TxPSOF

Transmit - Change of Port Indicator Input/Transmit - Start of PPP Packet in

Chunk Mode:

The function of this input pin depends upon whether the XRT79L71 has been

configured to operate in the Packet Mode or Cell-Chunk Mode.

Packet Mode - TxTSX TxTSX - Transmit POS-PHY Interface - Change of

Port Indicator Output (POS-PHY Level 3, Packet Mode only):

The Link-Layer processor pulses this input pin "High" when an in-band port

address is present on the TxPData[15:11] bus input pins. When this input pin

and TxPENB are both set "High" then the value of TxPData[15:11] is the

address value of the TxFIFO (Transmit POS-PHY Port) to be selected. Subse-

quent write operations, into TxPData[15:0] will fill the TxFIFO (within the Trans-

mit POS-PHY Port) corresponding to this particular in-band address.

Chunk Mode - TxPSOF - Transmit Start of Packet Input Indicator:

The Link Layer processor pulses this input pin "High" in order to indicate that the

first byte (or 16-bit word) of a given Packet is placed on the TxPData[15:0] pins.

NOTE: This input pin is only active if the XRT79L71 has been configured to

operate in the POS-PHY Level 3, Packet Mode or in the Chunk Mode. If

the user intends to operate the XRT79L71 in any other mode, then the

user should tie this input pin to GND.

TxUClkO/

TxPClkO

Transmit UTOPIA Interface Clock/Transmit POS-PHY Interface Clock Out-

put:

This output is derived from an internal PLL.

TxUClk/

TxPClk

Transmit UTOPIA Interface Clock/Transmit POS-PHY Interface Clock Input:

The function of this input pin depends upon whether the XRT79L71 has been

configured to operate in the ATM UNI or in the PPP Mode.

ATM UNI Mode - TxUClk - Transmit UTOPIA Interface - Clock Input pin:

The Transmit UTOPIA Interface clock is used to latch the data on the Transmit

UTOPIA Data bus, into the Transmit UTOPIA Interface block. This clock signal

is also used as the timing source for circuitry used to process the ATM cell data

into and through the TxFIFO.

During Multi-PHY operation, the data on the Transmit UTOPIA Address bus pins

is sampled on the rising edge of TxUClk.

PPP Mode - TxPClk - Transmit POS-PHY Interface - Clock Input pin:

The Transmit POS-PHY Interface clock is used to latch the data on the Transmit

POS-PHY Data bus, into the Transmit POS-PHY Interface block. This clock sig-

nal is also used as the timing source for circuitry used to process the Packet data

into and through the TxFIFO.

NOTES:

The XRT79L71 can support TxUClk or TxPClk clock frequencies of up

to 50MHz.

This input pin is inactive and should be tied to GND if the user

configures the XRT79L71 to operate in either the Clear-Channel

Framer or in the High-Speed HDLC Controller Modes.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB Datasheet(PDF) 33 Page - Exar Corporation

XRT79L71IB Datasheet(HTML) 33 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL