XRT79L71IB datasheet(47/109 Pages) EXAR

47 / 109 page

XRT79L71

REV. 1.0.0

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

RxUClav/RxPPA

Receive UTOPIA - Cell Available/Receive POS-PHY Interface - Packet

Available:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the ATM UNI or PPP Mode.

ATM UNI Mode - RxUClav - Receive UTOPIA Interface - Cell Available Indi-

cator Output:

The Receive UTOPIA Interface block will assert this output pin in order to indi-

cate that the RxFIFO has some ATM cell data that needs to be read out by the

ATM Layer Processor. This signal will be asserted (e.g., toggles to a logic

"High" level) if the RxFIFO contains at least one full ATM cell of data. This sig-

nal toggle "Low" if the RxFIFO is depleted of data, or if it contains less than one

full cell of data. The exact behavior of the RxUClav output pin, as a function of

UTOPIA Level is presented below.

Multi-PHY Operation - UTOPIA Level 2:

When the XRT79L71 is operating in a Multi-PHY Application and is configured

to operate in the UTOPIA Level 2 Mode, then this signal will be tri-stated until

the RxUClk cycle following the assertion of a valid address on the Receive

UTOPIA Address bus input pins (e.g., if the contents on the Receive UTOPIA

Address bus pins , RxUAddr[4:0], match that which have been assigned to this

particular Receive UTOPIA Interface block). Afterwards, this output pin will be

driven either "High" or "Low" depending upon the current fill status of the

RxFIFO.

Multi-PHY Operation - UTOPIA Level 3:

When the XRT79L71 is operating in a Multi-PHY Application, then this signal

will be tri-stated until two RxUClk cycles following the assertion of a valid

address on the Receive UTOPIA Address bus input pins (e.g., if the contents of

the Receive UTOPIA Address bus input pins, RxUAddr[4:0], match that which

have been assigned to this particular Receive UTOPIA Interface block). After-

wards, this output pin will be driven either "High" or "Low" depending upon the

current fill status of the RxFIFO.

PPP Mode - RxPPA - Receive POS-PHY Interface - Packet Available Indica-

tor Output

The XRT79L71 will drive this output pin "High" whenever a (programmable)

number of bytes of incoming PPP Packet data are available to be read from the

RxFIFO by the Link Layer Processor. The exact behavior of the RxPPA output

pin, as a function of POS-PHY Level is presented below.

POS-PHY Level 2:

When the XRT79L71 is configured to operate in the POS-PHY Level 2 Mode,

then this signal will be tri-stated until the RxPClk cycle following the assertion of

a valid address on the Receive POS-PHY Address bus input pins (e.g., if the

contents on the Receive POS-PHY Address bus pins, RxPAddr[4:0], match that

which have been assigned to this particular Receive POS-PHY Interface block).

Afterwards, this output pin will be driven either "High" or "Low" depending upon

the current fill status of the RxFIFO.

POS-PHY Level 3:

When the XRT79L71 is configured to operate in the POS-PHY Level 3 Mode,

then this signal will be tri-stated until two RxPClk cycles following the assertion

of a valid address on the Receive POS-PHY Address bus input pins (e.g., if the

contents on the Receive POS-PHY Address bus pins, RxPAddr[4:0], match that

which have been assigned to this particular Receive POS-PHY Interface block).

Afterwards, this output pin will be driven either "High" or "Low" depending upon

the current fill status of the RxFIFO.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB Datasheet(PDF) 47 Page - Exar Corporation

XRT79L71IB Datasheet(HTML) 47 Page - Exar Corporation

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