XRT79L71IB datasheet(32/109 Pages) EXAR

32 / 109 page

XRT79L71

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0

TxUSoC/

TxPSoP/

TxPSoC

Transmit UTOPIA - Start of Cell Input/Transmit POS-PHY - Start of Packet

Input (Packet Mode)/Transmit POS-PHY - Start of Chunk Input (Chunk

Mode):

The function of this input signal depends upon whether the XRT79L71 has been

configured to operate in the ATM UNI Mode, the PPP Packet Mode, or in the

PPP Chunk Mode, as described below.

ATM UNI Mode Operation - TxUSoC TxUSoC - Transmit Start of Cell Indica-

tor Input:

This input pin is driven by the ATM Layer Processor and is used to indicate the

start of an ATM cell that is being transmitted from the ATM Layer Processor. This

input pin must be pulsed "High" whenever the first byte (or word) of a new cell is

present on the Transmit UTOPIA Data Bus (TxUData[15:0]). This input pin must

remain "Low" at all other times.

PPP Mode Operation - TxPSoP/TxPSoC

If the XRT79L71 has been configured to operate in the PPP Mode, then the role

of this input pin can be further sub-divided, depending upon whether the Trans-

mit POS-PHY Interface block has been configured to operate in the Packet

Mode, or in the Chunk Mode, as described below.

PPP Packet Mode Operation - TxPSoP (Transmit POS-PHY - Start of Packet

Input):

If the XRT79L71 has been configured to operate in the Packet-Mode, then the

Link Layer Processor must pulse this input pin "High" coincident to whenever it

places the very first byte (or 16-bit word) of a given packet onto the Transmit

POS-PHY Data Bus (TxPData[15:0]) input pins.

NOTE: The Link Layer Processor must keep this input pin "Low" at all other

times.

PPP Chunk Mode Operation - TxPSoC (Transmit POS-PHY - Start of Chunk

Input):

If the XRT79L71 has been configured to operate in the Chunk Mode, then the

Link Layer Processor must pulse this input pin "High" coincident to whenever it

places the very first byte (or 16-bit word) of a given Chunk onto the Transmit

POS-PHY Data Bus (TxPData[15:0]) input pins.

NOTES:

The Link Layer Processor must keep this input pin "Low" at all other

times.

This input pin is only valid if the XRT79L71 has been configured to

operate in the ATM UNI or PPP Modes. The user should tie this input

pin to GND to operate the XRT79L71 in either the Clear-Channel

Framer or in the High-Speed HDLC Controller Modes.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB Datasheet(PDF) 32 Page - Exar Corporation

XRT79L71IB Datasheet(HTML) 32 Page - Exar Corporation

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