XRT79L71IB datasheet(68/109 Pages) EXAR

68 / 109 page

XRT79L71

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0

• The Transmit PLCP Processor Block

• The Transmit DS3/E3 Framer Block

• The Transmit DS3/E3 LIU Block

• The Receive DS3/E3 LIU Block

• The Receive DS3/E3 Framer Block

• The Receive PLCP Processor Block

• The Receive LAPD Controller Block

• The Receive SSM Controller Block (E3, ITU-T G.832 Applications Only)

• The Receive Trail-Trace Message Controller Block (ITU-T G.832 Applications Only)

• The Receive FEAC Controller Block (DS3, C-bit Parity Applications Only)

• The Receive ATM Cell Processor Block

• The Receive Overhead Data Output Interface Block

• The Receive UTOPIA Interface Block

Each of these functional blocks is briefly discussed below.

These functional blocks will be discussed in

considerable detail throughout this data sheet.

The Transmit UTOPIA Interface Block

The purpose of the Transmit UTOPIA Interface block is to provide a standard UTOPIA Level 1, 2 or 3 interface

to the ATM Layer Processor, for writing in the contents of all Valid ATM cells, into the Transmit FIFO (TxFIFO).

The Transmit UTOPIA Interface Block can be configured to operate with either an 8 or 16-bit wide

Transmit UTOPIA Data bus.

NOTE:

The Transmit UTOPIA Interface block supports UTOPIA Level 3 from a signaling stand-point.

The Transmit

UTOPIA Interface Block (within the XRT79L71) still only supports a 16-bit wide (not 32-bit wide) UTOPIA Bus and

only operates at clock rates of up to 50MHz (not 100MHz).

The Transmit Overhead Data Input Interface block (not shown in Figure 4)

The purpose of the Transmit Overhead Data Input Interface block is to permit the user to externally insert his/

her own values for overheads bits into the outbound DS3/E3 data-stream.

The Transmit ATM Cell Processor Block

The purpose of the Transmit ATM Cell Processor block is to read out the contents of user cells that have been

written into the TxFIFO (via the Transmit UTOPIA Interface block); and perform the following functions.

• Optionally Compute and Verify the HEC byte of each cell written into the TxFIFO

• To optionally discard all incoming ATM cells that contain HEC byte errors

• To optionally compute and insert the HEC byte into the fifth octet position, within each ATM cell that is written

into the TxFIFO

• To optionally filter User Cells (that are read out from the TxFIFO) by either discarding these User Cells, or by

replicating them and routing the copies of these cells to the Transmit Cell Extraction Buffer

• To insert cells (residing within the Transmit Cell Insertion Buffer) into the Transmit Data Path anytime the

TxFIFO is depleted of user cells

• To generate Idle Cells anytime the TxFIFO and the Transmit Cell Insertion Buffer are depleted of User cells

• To route the composite stream of valid and idle cells to either the Transmit PLCP Processor or the Transmit

DS3/E3 Framer Block.

The Transmit FEAC Controller Block (DS3, C-bit Parity Applications Only)

XRT79L71IB Datasheet(PDF) 68 Page - Exar Corporation

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